Looking for a VHDL or Verilog RAM Model that modles Common R

[Robert Posey]

Dear Gentle Persons,
Does anyone know where I could get a Verilog or VHDL RAM Model that models
common RAM Faults like Stuck At Faults on the Address, Data Lines, Stuck Ram
Cells, Coupling faults Etc?

I would also be interested in Verilog or VHDL implementation of a March SS
RAM Test, or any March type RAM Test.

Robert Posey