Looking for a FPGA board

T

Thomas Heller

Guest
I'm looking for a FPGA OEM module for analog signal processing
which contains the following:

- medium size spartan 3 or spartan 6 FPGA
- 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution
- 2 DACs, sampling rate > 50 MHz, 16 bit resolution
- plus quite some digital I/O lines
- on-board memory would be a plus, but it is not required

Does such a board exist in the price range up to 500 USD?

Thanks,
Thomas
 
I'm looking for a FPGA OEM module for analog signal processing
...

Analog(ue) signal process normally involves a lot of Op Amps from whic
filters, multipliers, differentiators, integrators and similar can b
constructed. No ADCs or DACs.

If you want to do digital signal processing, an FPGA with a lot of MA
blocks (such as the DSP48 in Xilinx FPGAs) is what you will need.


---------------------------------------
Posted through http://www.FPGARelated.com
 
Am 13.07.2011 08:50, schrieb Thomas Heller:
I'm looking for a FPGA OEM module for analog signal processing
which contains the following:

- medium size spartan 3 or spartan 6 FPGA
- 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution
- 2 DACs, sampling rate > 50 MHz, 16 bit resolution
- plus quite some digital I/O lines
- on-board memory would be a plus, but it is not required

Does such a board exist in the price range up to 500 USD?

Am 13.07.2011 11:44, schrieb RCIngham:
Analog(ue) signal process normally involves a lot of Op Amps from which
filters, multipliers, differentiators, integrators and similar can be
constructed. No ADCs or DACs.

If you want to do digital signal processing, an FPGA with a lot of MAC
blocks (such as the DSP48 in Xilinx FPGAs) is what you will need.
Of course I meant digital signal processing ;-).
That is the point of the ADCs and DACs connected to the FPGA.
 
If it's a one off then probably not. But of it is anything more e.g.
for an OEM manufacturing cycle we might be able to do something. We
are working on a few things like this.

John Adair
Enterpoint Ltd.

On Jul 13, 7:50 am, Thomas Heller <thel...@ctypes.org> wrote:
I'm looking for a FPGA OEM module for analog signal processing
which contains the following:

- medium size spartan 3 or spartan 6 FPGA
- 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution
- 2 DACs, sampling rate > 50 MHz, 16 bit resolution
- plus quite some digital I/O lines
- on-board memory would be a plus, but it is not required

Does such a board exist in the price range up to 500 USD?

Thanks,
Thomas
 
On 07/12/2011 11:50 PM, Thomas Heller wrote:
I'm looking for a FPGA OEM module for analog signal processing
which contains the following:

- medium size spartan 3 or spartan 6 FPGA
- 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution
- 2 DACs, sampling rate > 50 MHz, 16 bit resolution
- plus quite some digital I/O lines
- on-board memory would be a plus, but it is not required

Does such a board exist in the price range up to 500 USD?
_Dig_ through Xilinx's and Avnet's web pages. The last time I did real
FPGA design Xilinx pointed you to Avnet for a Spartan 6 board, and that
board had a dock for a daughter card, and Avnet had a _bazillion_
daughter cards.

A daughter card with ADC and DAC would be a no-brainer. At the speeds
you're looking for, you should probably stick the keyword "video" into
your search terms, look carefully at the data conversion hardware to
make sure it isn't specific to some video mode, and make sure you're
sitting down when you look at the price.

Here: this only misses your target price by a factor of 8:
http://www.xilinx.com/products/boards-and-kits/AES-V6DSP-LX240T-G.htm.

This one is well within your price range, but I didn't look to see how
fast the data conversion is:
http://www.xilinx.com/products/boards-and-kits/HW-SPAR3A-SK-UNI-G.htm

You get the idea. Good luck.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
You would probably be best just to buy a card with an FMC connector an
develop your own daughter board.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
On 13 Jul., 11:44, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

Analog(ue) signal process normally involves a lot of Op Amps from which
filters, multipliers, differentiators, integrators and similar can be
constructed. No ADCs or DACs.
This is an ambiguity in english language. Analog signal processing
could be:
a) analog processing of a signal
b) processing of an analog signal

b) can be performed by digitization followed by digital processing

The standard example of this language construct is the "german
prisoner of war camp",
where you can't tell whether the prisoners or the guards are german.

Kolja
 
- medium size spartan 3 or spartan 6 FPGA
- 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution
- 2 DACs, sampling rate > 50 MHz, 16 bit resolution
- plus quite some digital I/O lines
- on-board memory would be a plus, but it is not required
Check terasic:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=278&PartNo=1
or
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=360&PartNo=1

then any development kit which You like and can afford from Altera, which
has HSMC connector.
 
Kolja Sulimma <ksulimma@googlemail.com> wrote:

On 13 Jul., 11:44, "RCIngham"
robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

Analog(ue) signal process normally involves a lot of Op Amps from which
filters, multipliers, differentiators, integrators and similar can be
constructed. No ADCs or DACs.

This is an ambiguity in english language. Analog signal processing
could be:
a) analog processing of a signal
b) processing of an analog signal

b) can be performed by digitization followed by digital processing

The standard example of this language construct is the "german
prisoner of war camp",
where you can't tell whether the prisoners or the guards are german.
Which is why they invented context.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
 
Am 13.07.2011 20:44, schrieb maxascent:
You would probably be best just to buy a card with an FMC connector and
develop your own daughter board.
FMC, PMC, XMC, HSMC - a lot of 'standards'. However, this is one
possibility.

Thanks,
Thomas
 
Am 14.07.2011 14:03, schrieb scrts:
- medium size spartan 3 or spartan 6 FPGA
- 2 ADCs, sampling rate> 50 MHz, at least 14 (better 16) bit resolution
- 2 DACs, sampling rate> 50 MHz, 16 bit resolution
- plus quite some digital I/O lines
- on-board memory would be a plus, but it is not required

Check terasic:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=278&PartNo=1
or
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=360&PartNo=1

then any development kit which You like and can afford from Altera, which
has HSMC connector.
These add-on boards really look useful!

Once I needed such a board several years ago, I bought an ADC
evaluation board from linear technology, together with an so-called
Fast DAAC evaluation kit, and modified them to support DC coupling,
direct access to the build-in FPGA, and added a DAC myself as you
can see in this photo (the dac in on the solder side of the board):

http://starship.python.net/crew/theller/IMG_20110714_092433.jpg

It was quite some work but worked fine in the end, but I would
try to avoid this 'hack' in the future.

I found another thing that seems exactly what I need, and it
is only 3 times the price that I had in mind (I must admit
that my price expectations were somewhat naive):

USRP 200N from ettus research LLC:
around 1500$, Spartan 3A DSP FPGA, dual 100 MS/s 14 bit ADC,
dual 400 MS/s 16-bit DAC, DC coupled, 30 MHz Bandwidth, ...

http://www.ettus.com/products

Thanks again,
Thomas
 
Once I needed such a board several years ago, I bought an ADC
evaluation board from linear technology, together with an so-called
Fast DAAC evaluation kit, and modified them to support DC coupling,
direct access to the build-in FPGA, and added a DAC myself as you
can see in this photo (the dac in on the solder side of the board):

http://starship.python.net/crew/theller/IMG_20110714_092433.jpg
Maybe You're interested in software defined radio? I've got Stratix II GX
devkit, so I'm also searching for good addon board with fast ADCs and DACs.
That's why I've stopped at terasic site. Basically, now I am on the
crossroad to buy a manufactured board or do my own. I have a hope to run
four separate ADCs, each sampled from the same clock source, but +90deg
phase. I am not sure if this approach would be correct. Just brainstorming
now :)
 
On 07/14/2011 05:01 PM, scrts wrote:
Once I needed such a board several years ago, I bought an ADC
evaluation board from linear technology, together with an so-called
Fast DAAC evaluation kit, and modified them to support DC coupling,
direct access to the build-in FPGA, and added a DAC myself as you
can see in this photo (the dac in on the solder side of the board):

http://starship.python.net/crew/theller/IMG_20110714_092433.jpg

Maybe You're interested in software defined radio? I've got Stratix II GX
devkit, so I'm also searching for good addon board with fast ADCs and DACs.
That's why I've stopped at terasic site. Basically, now I am on the
crossroad to buy a manufactured board or do my own. I have a hope to run
four separate ADCs, each sampled from the same clock source, but +90deg
phase. I am not sure if this approach would be correct. Just brainstorming
now :)
If you're looking for a way to get quadrature demodulation when you
can't get a fast enough ADC, that is certainly theoretically correct.

You run into problems with mismatch between the ADCs, though. With one
fast ADC it's safe to assume that the sampling delay, offset, &c. of
each "channel" is the same -- because it's all measured from the same
ADC. You can't assume that when it's four ADCs, so you end up with
offsets and phase shifts in your demodulated data.

And no, I don't know how much -- run the numbers yourself!!

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
Am 15.07.2011 02:01, schrieb scrts:
Once I needed such a board several years ago, I bought an ADC
evaluation board from linear technology, together with an so-called
Fast DAAC evaluation kit, and modified them to support DC coupling,
direct access to the build-in FPGA, and added a DAC myself as you
can see in this photo (the dac in on the solder side of the board):

http://starship.python.net/crew/theller/IMG_20110714_092433.jpg

Maybe You're interested in software defined radio? I've got Stratix II GX
devkit, so I'm also searching for good addon board with fast ADCs and DACs.
That's why I've stopped at terasic site. Basically, now I am on the
crossroad to buy a manufactured board or do my own. I have a hope to run
four separate ADCs, each sampled from the same clock source, but +90deg
phase. I am not sure if this approach would be correct. Just brainstorming
now :)


No, I'm planning to build some kind of lock-in amplifier:
Measure the amplitude and phase of a signal in the presence
of lots of noise.
Totally different application than software defined radio, but it
seems I need the same hardware for that.

Thomas
 
In article <U4ydnRevfKpmUoLTnZ2dnUVZ_hOdnZ2d@web-ster.com>,
Tim Wescott <tim@seemywebsite.com> writes:

[4 channels offset by 90 degeres]

You run into problems with mismatch between the ADCs, though. With one
fast ADC it's safe to assume that the sampling delay, offset, &c. of
each "channel" is the same -- because it's all measured from the same
ADC. You can't assume that when it's four ADCs, so you end up with
offsets and phase shifts in your demodulated data.
Can I correct for that by feeding in a clean signal, collecting
a lot of data, and thinking about it?


--
These are my opinions, not necessarily my employer's. I hate spam.
 
If you're looking for a way to get quadrature demodulation when you can't
get a fast enough ADC, that is certainly theoretically correct.

You run into problems with mismatch between the ADCs, though. With one
fast ADC it's safe to assume that the sampling delay, offset, &c. of each
"channel" is the same -- because it's all measured from the same ADC. You
can't assume that when it's four ADCs, so you end up with offsets and
phase shifts in your demodulated data.
Well, I suppose one fast ADC would be much better, but such fast device
would cost a lot. Basically, I believe that if I would use four same chips,
clock as mentioned before and set the adc_start_conversion command properly,
then the delay, offset, etc, would be the same for them all and as mentioned
in datasheet. E.g. cheap DSOs use the same technique, but I am not sure
about ADC clock there.
 
On 2011-07-15, Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote:
Can I correct for that by feeding in a clean signal, collecting
a lot of data, and thinking about it?
I know that there has been some research in this area and this kind
of technology is also commercially available. (Some people from another
part of my university have started a quite successful company based
on this kind of technology for example.)

Anyway, if you want to do this as a learning experience/hobbyist project
or something similar I'd say go for it. You might want to search for
papers on "time interleaved A/D converters" before deciding to do so
though.

If you are doing this for commercial reasons you are probably better
off buying a faster ADC since it will be a lot easier to get that
working correctly than what you are proposing. You'll save yourself
some development time and perhaps also some lawyer time (since I'm
guessing that there are quite a few patents in this area that you
would either have to work around or work out a licensing deal for).

Anyway, good luck with your project!

regards
/Andreas
 

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