LogicAnalyzer ispTracy

[Andrés]

Hi,

I am trying to implement a debug template in an EC-FPGA (LFEC20E) with
the Lattice ispTRACY IP Manager.

I am facing some problems. Maybe someone of you has experienced the same
and can lead me into the right direction.

Here are the steps I perform:

1. In the ispLEVER Project Navigator I open under TOOLS the ispTRACY IP
Manager
2. In the ispTRACY IP Manager I define the RAM depth etc. under
CUSTOMIZE, then I click GENERATE to generate the file.
3. In the CORE LINKER I can connect the signals I want to look at with
the generated I/Os of the generated template.
When clicking OK a new top level file is generated
("eval_ddr_top_test_debug.vhd")

When importing this new top level file in the Project Navigator I see
that in the new top level file there is instantiated a component
"test_debug.vhd". But this file is missing. Instead there is just a file
"test_debug_tmpl.vhd" which can only be imported as a package.
So the component is missing.

Can someone tell me what went wrong or where to find the missing file?

Rgds
Andrés

 

[cas7406@yahoo.com]

Andrés wrote:

Hi,

I am trying to implement a debug template in an EC-FPGA (LFEC20E)
with
the Lattice ispTRACY IP Manager.

I am facing some problems. Maybe someone of you has experienced the
same
and can lead me into the right direction.

Here are the steps I perform:

1. In the ispLEVER Project Navigator I open under TOOLS the ispTRACY
IP
Manager
2. In the ispTRACY IP Manager I define the RAM depth etc. under
CUSTOMIZE, then I click GENERATE to generate the file.
3. In the CORE LINKER I can connect the signals I want to look at
with
the generated I/Os of the generated template.
When clicking OK a new top level file is generated
("eval_ddr_top_test_debug.vhd")

When importing this new top level file in the Project Navigator I see

that in the new top level file there is instantiated a component
"test_debug.vhd". But this file is missing. Instead there is just a
file
"test_debug_tmpl.vhd" which can only be imported as a package.
So the component is missing.

Can someone tell me what went wrong or where to find the missing
file?

Rgds
Andrés

Andres,

What you have done are the correct steps and you can keep going. The
"test_deubg.vhd" is a component generated by the linker to interconnect
the signals that you want to debug. There is no need to access to this
component (you can look at the respective .edi file generated).
Therefore, once you import the top level file to your project, this
component will be imported as well (ignore the red question mark) and
you will be able to generate the respective bitstream to start the
debug session (ispTRACY Logic Analyzer).

rgds,

cristian