Logic Simulation Question : Finding the transitions in each

[Sreekumar]

Hi,

I have a gate level verilog code. I would like to simulate it with
some inputs and find out which nodes within the logic block went from
0->1 and which went from 1->0. Which verilog simulator would be a good
one to do this?

Thanks for the help in advance.

Sreekumar

 

[Neo]

try modelsim, but I am not sure it will do exactly as you require.