Logic optimization at synthesis.

K

kumar

Guest
Hi All,

I have a simple counter, the code is given below.

always @(posedge sysclk) //sysclk period @ 50 ns
if (reset)
counter <= 4'b0000;
else if (counter == 4'd13) //counter is of type reg
counter <= 4'b0000;
else if (!sig1 && sig1_q) //sig1 period @ 10us and sig1_q is the
delayed input of sig1
counter <= counter + 4'b0001;
else if (counter != 4'd0)
counter <= counter + 4'b0001;

I have run the simulation, the simulation result is as expected, the
counter will be in the zero state '0', when there is a change in the
sig1 going from high to low the counter will increment by '1'. and
then counts upto 13 and resets back to '0' till the sig1 changes from
high to low.

The problem now is that, i do a synthesis with synplify_pro, and the
resultant file is taken to a FPGA, when i see this counter in the LA
(logic analyser), the counter will be 'b1 and when there is a change
in the "sig1" signal, the counter increments in odd values, ie., from
1 -> 3 -> 5 -> 7 ......

Your inputs are very valuable.

Thanks,
Regards,
Kumar
 
kumar wrote:
Hi All,

I have a simple counter, the code is given below.

always @(posedge sysclk) //sysclk period @ 50 ns
if (reset)
counter <= 4'b0000;
else if (counter == 4'd13) //counter is of type reg
counter <= 4'b0000;
else if (!sig1 && sig1_q) //sig1 period @ 10us and sig1_q is the
delayed input of sig1
counter <= counter + 4'b0001;
else if (counter != 4'd0)
counter <= counter + 4'b0001;

I have run the simulation, the simulation result is as expected, the
counter will be in the zero state '0', when there is a change in the
sig1 going from high to low the counter will increment by '1'. and
then counts upto 13 and resets back to '0' till the sig1 changes from
high to low.

The problem now is that, i do a synthesis with synplify_pro, and the
resultant file is taken to a FPGA, when i see this counter in the LA
(logic analyser), the counter will be 'b1 and when there is a change
in the "sig1" signal, the counter increments in odd values, ie., from
1 -> 3 -> 5 -> 7 ......

Your inputs are very valuable.

Thanks,
Regards,
Kumar
Have you tried simulating with the generated netlist? Synplify has an
Click to expand...
option to genertating a .v gate-level file in addition to the EDF file.
 
Jason Zheng wrote:
kumar wrote:
Hi All,

I have a simple counter, the code is given below.

always @(posedge sysclk) //sysclk period @ 50 ns
if (reset)
counter <= 4'b0000;
else if (counter == 4'd13) //counter is of type reg
counter <= 4'b0000;
else if (!sig1 && sig1_q) //sig1 period @ 10us and sig1_q is the
delayed input of sig1
counter <= counter + 4'b0001;
else if (counter != 4'd0)
counter <= counter + 4'b0001;

I have run the simulation, the simulation result is as expected,
the
counter will be in the zero state '0', when there is a change in
the
sig1 going from high to low the counter will increment by '1'. and
then counts upto 13 and resets back to '0' till the sig1 changes
from
high to low.

The problem now is that, i do a synthesis with synplify_pro, and
the
resultant file is taken to a FPGA, when i see this counter in the
LA
(logic analyser), the counter will be 'b1 and when there is a
change
in the "sig1" signal, the counter increments in odd values, ie.,
from
1 -> 3 -> 5 -> 7 ......

Your inputs are very valuable.

Thanks,
Regards,
Kumar
Have you tried simulating with the generated netlist? Synplify has an

option to genertating a .v gate-level file in addition to the EDF
file.
Click to expand...

Can U post the netlist?
 
kumar wrote:
(snip)
always @(posedge sysclk) //sysclk period @ 50 ns
if (reset)
counter <= 4'b0000;
else if (counter == 4'd13) //counter is of type reg
counter <= 4'b0000;
else if (!sig1 && sig1_q) //sig1 period @ 10us and sig1_q is the
delayed input of sig1
counter <= counter + 4'b0001;
else if (counter != 4'd0)
counter <= counter + 4'b0001;

I have run the simulation, the simulation result is as expected, the
counter will be in the zero state '0', when there is a change in the
sig1 going from high to low the counter will increment by '1'. and
then counts upto 13 and resets back to '0' till the sig1 changes from
high to low.

The problem now is that, i do a synthesis with synplify_pro, and the
resultant file is taken to a FPGA, when i see this counter in the LA
(logic analyser), the counter will be 'b1 and when there is a change
in the "sig1" signal, the counter increments in odd values, ie., from
1 -> 3 -> 5 -> 7 ......
Click to expand...
It looks fine to me. Can you look at the logic generated by
the synthesis tools? For example, Quartus has a tool called
RTL viewer (not in the free version, though) which will generate a
schematic logic diagram from the netlist.

-- glen
 
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