Logic implementation in SRAM/OTP FPGAs

[lenz]

Hello,

I have a question concerning the logic implementation techniques of
SRAM FPGAs and OTP FPGAs.

Logic in Xilinx FPGAs is implemented in LUTs. Logic in Quicklogic
FPGAs is implemented in a multiplexer structure.

Why does these two programming technologies use different techniques
to implement logic ?

Thanks in advance,
Mark Lenz

 

[Mario Trams]

Hi Mark,

I have a question concerning the logic implementation techniques of
SRAM FPGAs and OTP FPGAs.

Logic in Xilinx FPGAs is implemented in LUTs. Logic in Quicklogic
FPGAs is implemented in a multiplexer structure.

Why does these two programming technologies use different techniques
to implement logic ?

You mean because Quicklogic uses an OTP-Solution and Xilinx devices
are reprogramable?

I don't know the Quicklogic devices in detail, but I guess they are
using so-called Antifuse Technology.

One reason for such solutions is speed. In an SRAM/EEPROM-based
device the junctions of the interconnect are made by transfergates
and/or multiplexers. This costs time. In antifuse technology,
connections are created more or less statically during programming.

Another advantage of antifuse over the other technologies is that
you do not need to have a memory cell that says whether some
switch is "on" or "off". That is, you save chip area which makes
it cheaper for production. Less power is needed as well.

The reason why logic is implemented in a different manner might
be induced by the basic technology. In an SRAM-based device it
is perhaps more efficient to go the LUT-way. Another interesting
side-effect here is that one can use the LUTs as small RAM-blocks
in his design.

While a LUT could be made well out of antifuse cells, a multiplexer
structure yields perhaps to better speed characteristics. But I'm
not the expert here.

Regards,
Mario