Logic Data Types

[Simon Hobbs]

Hello all,
Bare with me, but I'm new to HDL and I'm debugging someone else's
commented code.

There is a line for declaring logic types that I keep coming across in a
specific module, but haven't seen in any verilog literature. Its as follows:

(* keep = 1 *) logic [SIZE-1:0] varName;

If anyone could point me towards some literature that covers this, it
would be greatly appreciated.

 

[Simon Hobbs]

On 6/12/2015 2:57 PM, Simon Hobbs wrote:

Hello all,
Bare with me, but I'm new to HDL and I'm debugging someone else's
commented code.

There is a line for declaring logic types that I keep coming across in a
specific module, but haven't seen in any verilog literature. Its as
follows:

(* keep = 1 *) logic [SIZE-1:0] varName;

If anyone could point me towards some literature that covers this, it
would be greatly appreciated.

To be more specific, I don't know what (* keep = 1 *) is intended to do.
~Simon

 

[Johann Klammer]

On 06/13/2015 12:01 AM, Simon Hobbs wrote:

On 6/12/2015 2:57 PM, Simon Hobbs wrote:
Hello all,
Bare with me, but I'm new to HDL and I'm debugging someone else's
commented code.

There is a line for declaring logic types that I keep coming across in a
specific module, but haven't seen in any verilog literature. Its as
follows:

(* keep = 1 *) logic [SIZE-1:0] varName;

If anyone could point me towards some literature that covers this, it
would be greatly appreciated.
To be more specific, I don't know what (* keep = 1 *) is intended to do.
~Simon

It's an attribute. Like those pragmas for compilers, they are implementation dependent.
Could enable a pin keeper circuit....

 

[Gabor]

On 6/12/2015 8:45 PM, Johann Klammer wrote:

On 06/13/2015 12:01 AM, Simon Hobbs wrote:
On 6/12/2015 2:57 PM, Simon Hobbs wrote:
Hello all,
Bare with me, but I'm new to HDL and I'm debugging someone else's
commented code.

There is a line for declaring logic types that I keep coming across in a
specific module, but haven't seen in any verilog literature. Its as
follows:

(* keep = 1 *) logic [SIZE-1:0] varName;

If anyone could point me towards some literature that covers this, it
would be greatly appreciated.
To be more specific, I don't know what (* keep = 1 *) is intended to do.
~Simon
It's an attribute. Like those pragmas for compilers, they are implementation dependent.
Could enable a pin keeper circuit....

For Xilinx synthesis, the keep attribute prevents nets from being
optimized away during synthesis. It's not 100% effective, but
useful for example when you want a net to stick around even though
it has no loads. Then you can attach it to ChipScope using the
inserter. The mapper can still remove nets with a keep attribute,
and Xilinx has another "S" attribute (save) to prevent removal in
the mapping phase.

--
Gabor

 

[Kevin Neilson]

On Friday, June 12, 2015 at 3:57:51 PM UTC-6, Simon Hobbs wrote:

Hello all,
Bare with me, but I'm new to HDL and I'm debugging someone else's
commented code.

There is a line for declaring logic types that I keep coming across in a
specific module, but haven't seen in any verilog literature. Its as follows:

(* keep = 1 *) logic [SIZE-1:0] varName;

If anyone could point me towards some literature that covers this, it
would be greatly appreciated.

Anything in a (* *) is a meta-comment, and whether it is interpreted or ignored is tool-dependent.