Logic Accessible Clock

[valtih1978]

The Logic Accessible Clocks are entailed for example in
http://www.cisl.columbia.edu/courses/spring-2004/ee4340/restricted_handouts/xapp200.pdf.
I do not see much explanation of the concept. But, I would expect some when
sys_clk_fb is registered by in-sync clk2. Sinse both clocks switch at the
same time, the setup/hold time, the basics of HW design, are violated for
sure!

 

[Ed McGettigan]

On May 4, 11:48 am, valtih1978 <intel...@yandex.ru> wrote:

The Logic Accessible Clocks are entailed for example in  http://www.cisl.columbia.edu/courses/spring-2004/ee4340/restricted_ha....
I do not see much explanation of the concept. But, I would expect some when
sys_clk_fb is registered by in-sync clk2. Sinse both clocks switch at the
same time, the setup/hold time, the basics of HW design, are violated for
sure!

This was something unique to DDR SDRAM implementation in a now
obsolete FPGA family to allow for a local clock in the fabric.
Improvements in modern FPGA families make this technique obsolete.

In this implementation the clock input does goes to the data input of
a register, but the clock of this register is from a DCM 2X output and
there is delay differences between the two that allows for this clock
to be captured and then used as data with the logic.

Ed McGettigan
--
Xilinx Inc.