Log implementation in vhdl

Hi all, how can we implement logarithm of a number in VHDL.
any tips ??? thanx

 

[TigerJade]

LUT?

 

Thanks.

Jonathan Bromley wrote:

On 24 Jun 2005 07:36:14 -0700, praveen.rajaretnam@gmail.com wrote:

Hi all, how can we implement logarithm of a number in VHDL.
any tips ??? thanx

A normaliser counts leading zeros and extracts the mantissa,
so giving the logarithm to within 6dB. Typically you can
then do table lookup on the top few bits of the normalised
result, to get some more accuracy.

Obviously, it depends on the precision you need.

Standard methods such as Taylor series and CORDIC may also
be useful if you want really high precision. Once again,
it's MUCH easier if you normalise the number first, so that
you only need to find the log of a number in the range
0.5 to 1.0
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.