load on a clock signal in FPGA

[raj]

Hi,

I have a small doubt regarding the load seen by a primary global clock
buffer in a FPGA.

My design consumes 1940 flops out of 3072,and also the load in the
BUFGP shows only 1940 flops .I thought as the clock tree is pre-synthesized,
no matter how many flops are consumed, the clock signal is driven to each and
every flop.Can anybody comment,how it is disabled in unused flops so that
clock buffers do not see the load in unused flops.Is it same for GSR??

thanks
--raj

 

[Marc Randolph]

raj wrote:

Hi,

I have a small doubt regarding the load seen by a primary global clock
buffer in a FPGA.

My design consumes 1940 flops out of 3072,and also the load in the
BUFGP shows only 1940 flops .I thought as the clock tree is pre-synthesized,
no matter how many flops are consumed, the clock signal is driven to each and
every flop.Can anybody comment,how it is disabled in unused flops so that
clock buffers do not see the load in unused flops.Is it same for GSR??

Howdy Raj,

The tools are pretty smart about only activating the parts of the
clock tree that are needed - it is one way to save power. And yes, the
GSR would only be activated to the FF's that actually use it.

Marc

 

[Jon Elson]

raj wrote:

Hi,

I have a small doubt regarding the load seen by a primary global clock
buffer in a FPGA.

My design consumes 1940 flops out of 3072,and also the load in the
BUFGP shows only 1940 flops .I thought as the clock tree is pre-synthesized,
no matter how many flops are consumed, the clock signal is driven to each and
every flop.Can anybody comment,how it is disabled in unused flops so that
clock buffers do not see the load in unused flops.Is it same for GSR??


The clock tree GOES out to every FF, but it doesn't get CONNECTED to the FF

unless that flop needs that clock. So, there is some capacitive loading
from the stubs,
but not the loading of the FF's inputs on the flops not clocked from the
GCLK.
Anyway, one can presume Xilinx has run all versions of the chip with
every FF
on the entire chip clocked from the same GCLK, just to make sure the
clock tree
can handle that.

Jon