L
Lars
Guest
Hi all!
We are trying to use the LM9822CCWM Analog Front End to digitize the
output from a linear colour CCD but with poor result. Initially the
device did not output any digital data att all (all zeros). After
limiting the analog input voltage, (the reset puses from the CCD
exceeded the 5.3 V max input voltage), things looked a bit better, but
still all data bits after some time begin to exhibit transitions on
both edges of the clock and none resemble the expected data, going
gradually after several minutes running to no data output at all (all
zeros). It is not a thermal phenomena since a very breif power-off/
power-on restarts the behaviour from scratch.
My best clue after we got the analog voltage in hand was the we had a
clock reflection on MCLK causing false clocking on the wrong edge, but
that was not the case. Careful termination of MCLK had no effect.
The next clue is that the device is extreamly sensitive to over- and
undershots (deduced from the fact that behaviour changed when analog
input was limited). I do not have any simple way to verify this, short
of adding a buffer stage close to the device. We drive the clock
signals from a small FPGA (XC3S50AN) and the traces to the device are
quite long (approx 10 inches) due to mechanical limitations in the
application. I have limited the drive to minimum (2mA slow LVTTL
drivers, have also tested CMOS) and we are running at a fairly low
clock speed of 4MHz MCLK in 6 bytes per pixel colour mode, which is
the default setting, but there is moderate over- and undershoot on all
signals.
Va is 5V and Vd is 3.3V. Both are regulated by LDO's in series from
the same 12V source so they ought to ramp up in sync (verified on
scope).
Anyone out there with a clue as to what is going on? Did we break the
device when we had too large analog input or are there any quirks with
this device that we are missing in the data sheet? We have exactly
the same behaviour on the two different individualls we have tested so
far.
Regards, /Lars
P.S. Remove the obvious from my email address in case you want to
email me directly. D.S.
We are trying to use the LM9822CCWM Analog Front End to digitize the
output from a linear colour CCD but with poor result. Initially the
device did not output any digital data att all (all zeros). After
limiting the analog input voltage, (the reset puses from the CCD
exceeded the 5.3 V max input voltage), things looked a bit better, but
still all data bits after some time begin to exhibit transitions on
both edges of the clock and none resemble the expected data, going
gradually after several minutes running to no data output at all (all
zeros). It is not a thermal phenomena since a very breif power-off/
power-on restarts the behaviour from scratch.
My best clue after we got the analog voltage in hand was the we had a
clock reflection on MCLK causing false clocking on the wrong edge, but
that was not the case. Careful termination of MCLK had no effect.
The next clue is that the device is extreamly sensitive to over- and
undershots (deduced from the fact that behaviour changed when analog
input was limited). I do not have any simple way to verify this, short
of adding a buffer stage close to the device. We drive the clock
signals from a small FPGA (XC3S50AN) and the traces to the device are
quite long (approx 10 inches) due to mechanical limitations in the
application. I have limited the drive to minimum (2mA slow LVTTL
drivers, have also tested CMOS) and we are running at a fairly low
clock speed of 4MHz MCLK in 6 bytes per pixel colour mode, which is
the default setting, but there is moderate over- and undershoot on all
signals.
Va is 5V and Vd is 3.3V. Both are regulated by LDO's in series from
the same 12V source so they ought to ramp up in sync (verified on
scope).
Anyone out there with a clue as to what is going on? Did we break the
device when we had too large analog input or are there any quirks with
this device that we are missing in the data sheet? We have exactly
the same behaviour on the two different individualls we have tested so
far.
Regards, /Lars
P.S. Remove the obvious from my email address in case you want to
email me directly. D.S.