Link 2 modules

[Luiz Gustavo]

Hi,

How can I link to modules?
__________ __________
| | --------> mosi | |
--->lm | master | --------> sck | slave |
-->clock| | --------> ss | |
|_________| <------- miso |_________|

I try to do something like this:

module master (clock, lm, ss, sck, mosi, miso);

input wire miso;
input wire load_memory;
input wire clock;
output wire mosi;
output wire ss;
output wire sck;

/ ......


........\
endmodule

module slave(ss, sck, mosi, miso);

input wire ss;
input wire sck;
input wire mosi;
output wire miso;

/..................


..................\
endmodule

The input of master is output of slave, and vice versa.

The Quartus give me a error: "Ignored module slave at master.v,
becouse previous errors."

Thanks,
Gustavo

 

[Guenter]

On Jan 30, 8:02 pm, "Luiz Gustavo" <luizval...@gmail.com> wrote:

Hi,

How can I link to modules?
__________ __________
| | --------> mosi | |
--->lm | master | --------> sck | slave |
-->clock| | --------> ss | |
|_________| <------- miso |_________|

I try to do something like this:

module master (clock, lm, ss, sck, mosi, miso);

input wire miso;
input wire load_memory;
input wire clock;
output wire mosi;
output wire ss;
output wire sck;

[...]

Do you see that there is a mismatch. You specify input wire
load_memory, but it does not appear in the module interface list.
Instead you have lm there.

The Quartus give me a error: "Ignored module slave at master.v,
becouse previous errors."

Are there any options to get a more detailed error message? Maybe that
helps?

Just having those two modules does not connect them. You need to
instantiate them create some wires and connect the instances with
them.

 

Luiz Gustavo wrote:

Hi,

How can I link to modules?

You need another module that represents your
entire design. Then you instantiate a master and
slave module inside that, and connect them together
using wires declared in the top-level module.

In your block diagram, think of this module as the
block that goes around the entire design, or the
border around the entire block diagram.

It is possible to have multiple top-level blocks in
Verilog, but then you have no way to specify that
they are connected together.