Lines of code being ignored in my process constructs

Guest
When I simulate the following code using ISE, some of my signal
assignments are not being executed in some places, and in others
okay ? Also OVR_FLOW is being assigned a value of logic 1 as it
default value, when clearly it should be logic 0. Anyone know what is
happening ?



Below is my code, refer to <-- for comments.




entity RX_FIFO_WR_CONTROL is
Port ( data_clk : in STD_LOGIC;
data:in STD_LOGIC_VECTOR (7 downto 0);
frame_mrk : in STD_LOGIC;
rxdv: in STD_LOGIC;
fifo_full : in STD_LOGIC;
frame_good: in STD_LOGIC;
frame_bad: in STD_LOGIC;
fifo_wr_data: out STD_LOGIC_VECTOR (8 downto 0);
wr_fifo_en : out STD_LOGIC;
rst: IN STD_LOGIC);
end RX_FIFO_WR_CONTROL;

architecture RTL of RX_FIFO_WR_CONTROL is


type FIFO_CNTRL_STATE is
IDLE,WRITE_FIFO,WAIT_END,READ_FRAME_CONDITION,WRITE_FRAME_STATUS);
signal CURRENT_STATE,NEXT_STATE:FIFO_CNTRL_STATE;
signal OVR_FLOW: std_logic;
signal TEMP_DATA:STD_LOGIC_VECTOR (8 downto 0);
signal FRAME_STATUS:STD_LOGIC_VECTOR (8 downto 0);
signal data_present:integer range 0 to 2000;

begin


SYNC: process (data_clk,rst)
begin
if rising_edge(data_clk) then
if rst='1' then
current_state<=idle;
data_present<=0;
else
current_state<=next_state;
data_present<=1;
end if;
end if;

if data_clk='1' then
data_present<=1;
else
data_present<=0;
end if;
end process SYNC;



OUTPUT_DECODE: process
(current_state,frame_mrk,fifo_full,data_present)
begin
wr_fifo_en<='0';
TEMP_DATA<="000000000";
OVR_FLOW<='0';
FRAME_STATUS<="000000000";

if current_state = idle and frame_mrk = '1' then
wr_fifo_en<='1'; <--- this line is being ignored when in
idle state

and frame_mrk is logic 1 ?


TEMP_DATA(7 downto 0)<=data;
TEMP_DATA(8)<=frame_mrk;

end if;

if current_state=write_fifo and fifo_full<='0' then

TEMP_DATA(8)<=frame_mrk;
TEMP_DATA(7 downto 0)<=data;
TEMP_DATA(8)<=frame_mrk;
else
OVR_FLOW<='1'; <--- in the idle state OVR_FLOW defaults to

logic 1 not 0, it should only change to

logic 1 when fifo_full is logic 1 and in the

write_fifo state ?
wr_fifo_en<='0';
end if;

if frame_mrk='0' then
TEMP_DATA(8)<=frame_mrk;
wr_fifo_en<='0';
end if;

if current_state=wait_end and fifo_full<='1' then
OVR_FLOW<='1';
end if;

if current_state=read_frame_condition and data_present=1 then
FRAME_STATUS(8)<='0';
FRAME_STATUS(7)<=OVR_FLOW;
FRAME_STATUS(6)<=frame_good;
FRAME_STATUS(5)<=frame_bad;
FRAME_STATUS(4 downto 0)<="00000";
end if;

if current_state=write_frame_status then
wr_fifo_en<='1'; <--- this is excuted okay, despite wr_fifo_en
being

ignored in the idle state, why work here and not

there ?
TEMP_DATA<=FRAME_STATUS;
end if;

end process;

fifo_wr_data<=TEMP_DATA;

COMB: process (current_state,frame_mrk,rxdv)
begin
next_state<=current_state;
case current_state is
when idle =>
if frame_mrk='1' then
next_state<=write_fifo;
end if;
when write_fifo =>
if frame_mrk='0' then
next_state<= wait_end;
end if;
when wait_end =>
if rxdv='0' then
next_state<=read_frame_condition;
end if;
when read_frame_condition =>
next_state<=write_frame_status;
when write_frame_status =>
next_state<=idle;
when others =>
next_state <= idle;
end case;
end process COMB;

end RTL;
 
On Apr 3, 2:37 am, maurizio.gencare...@dsto.defence.gov.au wrote:
When I simulate the following code using ISE, some of my signal
assignments are not being executed in some places, and in others
okay ? Also OVR_FLOW is being assigned a value of logic 1 as it
default value, when clearly it should be logic 0. Anyone know what is
happening ?

Below is my code, refer to <-- for comments.

entity RX_FIFO_WR_CONTROL is
Port ( data_clk : in STD_LOGIC;
data:in STD_LOGIC_VECTOR (7 downto 0);
frame_mrk : in STD_LOGIC;
rxdv: in STD_LOGIC;
fifo_full : in STD_LOGIC;
frame_good: in STD_LOGIC;
frame_bad: in STD_LOGIC;
fifo_wr_data: out STD_LOGIC_VECTOR (8 downto 0);
wr_fifo_en : out STD_LOGIC;
rst: IN STD_LOGIC);
end RX_FIFO_WR_CONTROL;

architecture RTL of RX_FIFO_WR_CONTROL is

type FIFO_CNTRL_STATE is
IDLE,WRITE_FIFO,WAIT_END,READ_FRAME_CONDITION,WRITE_FRAME_STATUS);
signal CURRENT_STATE,NEXT_STATE:FIFO_CNTRL_STATE;
signal OVR_FLOW: std_logic;
signal TEMP_DATA:STD_LOGIC_VECTOR (8 downto 0);
signal FRAME_STATUS:STD_LOGIC_VECTOR (8 downto 0);
signal data_present:integer range 0 to 2000;

begin

SYNC: process (data_clk,rst)
begin
if rising_edge(data_clk) then
if rst='1' then
current_state<=idle;
data_present<=0;
else
current_state<=next_state;
data_present<=1;
end if;
end if;

if data_clk='1' then
data_present<=1;
else
data_present<=0;
end if;
end process SYNC;

OUTPUT_DECODE: process
(current_state,frame_mrk,fifo_full,data_present)
begin
wr_fifo_en<='0';
TEMP_DATA<="000000000";
OVR_FLOW<='0';
FRAME_STATUS<="000000000";

if current_state = idle and frame_mrk = '1' then
wr_fifo_en<='1'; <--- this line is being ignored when in
idle state

and frame_mrk is logic 1 ?

TEMP_DATA(7 downto 0)<=data;
TEMP_DATA(8)<=frame_mrk;

end if;

if current_state=write_fifo and fifo_full<='0' then

TEMP_DATA(8)<=frame_mrk;
TEMP_DATA(7 downto 0)<=data;
TEMP_DATA(8)<=frame_mrk;
else
OVR_FLOW<='1'; <--- in the idle state OVR_FLOW defaults to

logic 1 not 0, it should only change to

logic 1 when fifo_full is logic 1 and in the

write_fifo state ?
wr_fifo_en<='0';
end if;

if frame_mrk='0' then
TEMP_DATA(8)<=frame_mrk;
wr_fifo_en<='0';
end if;

if current_state=wait_end and fifo_full<='1' then
OVR_FLOW<='1';
end if;

if current_state=read_frame_condition and data_present=1 then
FRAME_STATUS(8)<='0';
FRAME_STATUS(7)<=OVR_FLOW;
FRAME_STATUS(6)<=frame_good;
FRAME_STATUS(5)<=frame_bad;
FRAME_STATUS(4 downto 0)<="00000";
end if;

if current_state=write_frame_status then
wr_fifo_en<='1'; <--- this is excuted okay, despite wr_fifo_en
being

ignored in the idle state, why work here and not

there ?
TEMP_DATA<=FRAME_STATUS;
end if;

end process;

fifo_wr_data<=TEMP_DATA;

COMB: process (current_state,frame_mrk,rxdv)
begin
next_state<=current_state;
case current_state is
when idle =
if frame_mrk='1' then
next_state<=write_fifo;
end if;
when write_fifo =
if frame_mrk='0' then
next_state<= wait_end;
end if;
when wait_end =
if rxdv='0' then
next_state<=read_frame_condition;
end if;
when read_frame_condition =
next_state<=write_frame_status;
when write_frame_status =
next_state<=idle;
when others =
next_state <= idle;
end case;
end process COMB;

end RTL;
Click to expand...

1) When you declare "FIFO_CNTRL_STATE", the opening "(" parenthses is
missing. I don't know if this causes a problem or not.
2) "if current_state=write_fifo and fifo_full<='0' then"
What are you trying to do with "fifo_full"? It's an input, so the
synthesis tool shouldn't allow you to assign '0' to it. The tool
should flag this statement as an error, unless it thinks you are
trying to see if "fifo_full" is less-than-or-equal to '0'.
3) "if current_state=wait_end and fifo_full<='1' then"
Same as above except '1' instead of '0'.

HTH
-Dave Pollum
 
maurizio.gencarelli@dsto.defence.gov.au wrote:
When I simulate the following code using ISE, some of my signal
assignments are not being executed in some places, and in others
okay ? Also OVR_FLOW is being assigned a value of logic 1 as it
default value, when clearly it should be logic 0. Anyone know what is
happening ?
Click to expand...
Your synchronous template should only
use the clock for the edge condition.


SYNC: process (data_clk,rst)
begin
if rising_edge(data_clk) then
if rst='1' then
current_state<=idle;
data_present<=0;
Click to expand...
-- assignment above is always overwritten below

else
current_state<=next_state;
data_present<=1;
Click to expand...
-- assignment above is always overwritten below

end if;
end if;

if data_clk='1' then
data_present<=1; -- overwrites above
else
data_present<=0; -- overwrites above
end if;
end process SYNC;
Click to expand...

-- Mike Treseler
 
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