library/design instance resolution

[Todd Walk]

(I don't have a simulator around to test this.)

In a design you have (psuedo-code):

module A
endmodule

module B
instance C
endmodule

In your library you have:

module A
endmodule

module C
instance A
endmodule

Which module A will be used for the instance in library cell C?
Will it use the design module A that it has already processed?
Or will it use the cell in the library?

Todd.

 

[Shalom Bresticker]

Design module A.

Shalom


Todd Walk wrote:

(I don't have a simulator around to test this.)

In a design you have (psuedo-code):

module A
endmodule

module B
instance C
endmodule

In your library you have:

module A
endmodule

module C
instance A
endmodule

Which module A will be used for the instance in library cell C?
Will it use the design module A that it has already processed?
Or will it use the cell in the library?

Todd.

--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478

 

[Ajeetha Kumari]

Hi Todd,

Todd Walk <todd_walk@mentor.com> wrote in message news:<3F1313F2.96969850@mentor.com>...

(I don't have a simulator around to test this.)

In a design you have (psuedo-code):

module A
endmodule

module B
instance C
endmodule

In your library you have:

module A
endmodule

module C
instance A
endmodule

I think it is tool dependent, let me explain why I think so before I
get any flame

1. If you use a compiled code simulator such as NCSIM and ASSUMING
that you compile design.module.A first and then library.module.A (in
to the same work library) and finally module C, NCSIM will pick up
library.module.A as that has been compiled the last and would have
over-written the previous image.

2. Things would be different if you different libraries to compile
into, of-course. Then I think NCSIM has some way of forcing which one
to pick (similar to CHDL/Verilog-2001 configuration, but less
powerful).

3. I haven't tried such a case in Modelsim, neither in VCS nor in VXL,
but I know that if you have 2 modules with same name, VCS & VXL would
exit with error.

Regards,
Ajeetha
http://www.noveldv.com

P.S. It is interesting to see that you have a @mentor.com e-mail ID
and say you don't have access to a simulator, no flame intended, just
curious as I know more and more individuals prefer using the FREE
version of Modelsim that comes with Webpack, I am a happy user of that
too

Which module A will be used for the instance in library cell C?
Will it use the design module A that it has already processed?
Or will it use the cell in the library?

Todd.

 

[Todd Walk]

Regards,
Ajeetha
http://www.noveldv.com

P.S. It is interesting to see that you have a @mentor.com e-mail ID
and say you don't have access to a simulator, no flame intended, just
curious as I know more and more individuals prefer using the FREE
version of Modelsim that comes with Webpack, I am a happy user of that
too

Well, I can get access to the model tech one, but then I have to deal
with the pita of getting the licensing, etc, set up. I should have mentioned
that what I really want is how XL does it, and there isn't any way I'll be
able to get ahold of it. Todd.

 

[Todd Walk]

Could you elaborate why? Is this with XL?

Using design module A seems like the wrong thing that
should be done here. (The library designer wouldn't be
able to control functionality, a simple name conflict will
cause a different module to be bound, it could introduce
unwanted order dependencies, and the ports of these
modules could even be different, which may or may not
report an error.)

OTOH, if the tool is using a simple single symbol table,
then this situation would happen. It would also give the
dubious benefit of allowing replacement of library cells
without physically modifying the library.


Shalom Bresticker wrote:

Design module A.

Shalom

Todd Walk wrote:

(I don't have a simulator around to test this.)

In a design you have (psuedo-code):

module A
endmodule

module B
instance C
endmodule

In your library you have:

module A
endmodule

module C
instance A
endmodule

Which module A will be used for the instance in library cell C?
Will it use the design module A that it has already processed?
Or will it use the cell in the library?