T
trescot@gmail.com
Guest
I am new to VHDL and I am really having a hard time with library and
packages. Well to include packages in verilog we just used `include
directive, but in VHDL, I guess we have to make a library and refer
thouse files w.r to those lib.
I have 3 packages that I am using in my design.
For simplification lets call it a_pkg.vhd , b_pkg.vhd, c_pkg.vhd.
Now my question is if all these packages is in the same folder as other
rtl, how should I include them in my other files? What is the use of
lib?
Thanks
Trescot
packages. Well to include packages in verilog we just used `include
directive, but in VHDL, I guess we have to make a library and refer
thouse files w.r to those lib.
I have 3 packages that I am using in my design.
For simplification lets call it a_pkg.vhd , b_pkg.vhd, c_pkg.vhd.
Now my question is if all these packages is in the same folder as other
rtl, how should I include them in my other files? What is the use of
lib?
Thanks
Trescot