F
Flemming Hansen
Guest
Hi,
In a school project I'm going to make 7 segment LED decoder with CoolRunner
II xc2c32a. There will be 3 inputs and 3 outputs to the CoolRunner. An
enable signal will enable the LEDs, CS to select the LED, and a 4 bit data.
I made the following VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LED_decoder is
Port ( E : in std_logic;
CS : in std_logic_vector(1 downto 0);
DATA : in std_logic_vector(3 downto 0);
LED1 : out std_logic_vector(6 downto 0);
LED2 : out std_logic_vector(6 downto 0);
LED3 : out std_logic_vector(6 downto 0));
end LED_decoder;
architecture Behavioral of LED_decoder is
begin
--DEC-to-seven-segment decoder
--
-- *** Common Anode
--
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3
--
process (E, CS, DATA)
begin
if (E='1') then
if(CS="01") then
case DATA is
when "0001" => LED1 <= "1111001"; --1
when "0010" => LED1 <= "0100100"; --2
when "0011" => LED1 <= "0110000"; --3
when "0100" => LED1 <= "0011001"; --4
when "0101" => LED1 <= "0010010"; --5
when "0110" => LED1 <= "0000010"; --6
when "0111" => LED1 <= "1111000"; --7
when "1000" => LED1 <= "1111111"; --8
when "1001" => LED1 <= "0010000"; --9
when others => LED1 <= "1000000"; --0
end case;
elsif(CS="10") then
case DATA is
when "0001" => LED2 <= "1111001"; --1
when "0010" => LED2 <= "0100100"; --2
when "0011" => LED2 <= "0110000"; --3
when "0100" => LED2 <= "0011001"; --4
when "0101" => LED2 <= "0010010"; --5
when "0110" => LED2 <= "0000010"; --6
when "0111" => LED2 <= "1111000"; --7
when "1000" => LED2 <= "1111111"; --8
when "1001" => LED2 <= "0010000"; --9
when others => LED2 <= "1000000"; --0
end case;
elsif(CS="11") then
case DATA is
when "0001" => LED3 <= "1111001"; --1
when "0010" => LED3 <= "0100100"; --2
when "0011" => LED3 <= "0110000"; --3
when "0100" => LED3 <= "0011001"; --4
when "0101" => LED3 <= "0010010"; --5
when "0110" => LED3 <= "0000010"; --6
when "0111" => LED3 <= "1111000"; --7
when "1000" => LED3 <= "1111111"; --8
when "1001" => LED3 <= "0010000"; --9
when others => LED3 <= "1000000"; --0
end case;
end if;
else
LED1 <= "1111111";
LED2 <= "1111111";
LED3 <= "1111111";
end if;
end process;
end Behavioral;
I get a warnin message that says that 7-bit latch for signal LED1, LED2 and
LED3. Syntax check says that the code is ok. But in Post-Fit VHDL Model
simulation with ModelSim there are some errors, I mean some undefined and
unexpected values. Any suggestion on what the cause could be? Or any
suggestion or examples for a code to the job?
Thanx in advance
In a school project I'm going to make 7 segment LED decoder with CoolRunner
II xc2c32a. There will be 3 inputs and 3 outputs to the CoolRunner. An
enable signal will enable the LEDs, CS to select the LED, and a 4 bit data.
I made the following VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LED_decoder is
Port ( E : in std_logic;
CS : in std_logic_vector(1 downto 0);
DATA : in std_logic_vector(3 downto 0);
LED1 : out std_logic_vector(6 downto 0);
LED2 : out std_logic_vector(6 downto 0);
LED3 : out std_logic_vector(6 downto 0));
end LED_decoder;
architecture Behavioral of LED_decoder is
begin
--DEC-to-seven-segment decoder
--
-- *** Common Anode
--
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3
--
process (E, CS, DATA)
begin
if (E='1') then
if(CS="01") then
case DATA is
when "0001" => LED1 <= "1111001"; --1
when "0010" => LED1 <= "0100100"; --2
when "0011" => LED1 <= "0110000"; --3
when "0100" => LED1 <= "0011001"; --4
when "0101" => LED1 <= "0010010"; --5
when "0110" => LED1 <= "0000010"; --6
when "0111" => LED1 <= "1111000"; --7
when "1000" => LED1 <= "1111111"; --8
when "1001" => LED1 <= "0010000"; --9
when others => LED1 <= "1000000"; --0
end case;
elsif(CS="10") then
case DATA is
when "0001" => LED2 <= "1111001"; --1
when "0010" => LED2 <= "0100100"; --2
when "0011" => LED2 <= "0110000"; --3
when "0100" => LED2 <= "0011001"; --4
when "0101" => LED2 <= "0010010"; --5
when "0110" => LED2 <= "0000010"; --6
when "0111" => LED2 <= "1111000"; --7
when "1000" => LED2 <= "1111111"; --8
when "1001" => LED2 <= "0010000"; --9
when others => LED2 <= "1000000"; --0
end case;
elsif(CS="11") then
case DATA is
when "0001" => LED3 <= "1111001"; --1
when "0010" => LED3 <= "0100100"; --2
when "0011" => LED3 <= "0110000"; --3
when "0100" => LED3 <= "0011001"; --4
when "0101" => LED3 <= "0010010"; --5
when "0110" => LED3 <= "0000010"; --6
when "0111" => LED3 <= "1111000"; --7
when "1000" => LED3 <= "1111111"; --8
when "1001" => LED3 <= "0010000"; --9
when others => LED3 <= "1000000"; --0
end case;
end if;
else
LED1 <= "1111111";
LED2 <= "1111111";
LED3 <= "1111111";
end if;
end process;
end Behavioral;
I get a warnin message that says that 7-bit latch for signal LED1, LED2 and
LED3. Syntax check says that the code is ok. But in Post-Fit VHDL Model
simulation with ModelSim there are some errors, I mean some undefined and
unexpected values. Any suggestion on what the cause could be? Or any
suggestion or examples for a code to the job?
Thanx in advance