learning systerm verilog

Hello Every One

I need your kind help for the sysstem verilog.

I want to learn System Verilog. But I am confused about how to start
and from where to start?

I know verilog and VHDL very well. I have a working knowledge of C.

Now I want to learn system verilog ,as I have to work in system
verilog.

So please help me how to start. Should I have to directly read the LRM
of the systemverilog ?? Or any book is available for the SV ?
I heard that C++ knowledge is necessary to learn SV ? So should I have
to start with C++ (as I dont know C++) ?

Is there any free tools availables for the SV ! ?

Regards,
Hemanth

 

[Ajeetha]

Depends on what you want to learn/use from SV. As you may know SV has 4
major portions:

SV Design --> Lot of enh over V2K
SV DPI --> Direct Programming Interface
SV Assertions --> Full fledges assertion language
SV TestBench --> A comprehensive HVL

There is quite a bit of material on the web, few are:

www.project-veripage.com
www.abv-sva.org

A google search will reveal lot more. If you have VCS/MTI/NC installed
(latest versions) their examples/documents will help a lot as well.

All depends on what you goal is with SV.

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[Jeremy Ralph]

For verification I think Object Orientation concepts such as objects,
classes, encapsulation, and inheritance would be useful. These OO
concepts are similar across most OOP languages.

Constrained random stimulus generation, assertions (for coverage, etc)
and interfaces provide many benefits over ole' Verilog. Don't think
C++ will help much with learning these... certainly knowing Vera or
Specman e would help with this.

I find the following links useful (the last of which Ajeetha already
mentioned) along with the docs/examples include with my simulator.

http://www.doulos.com/knowhow/sysverilog/tutorial/
http://www.project-veripage.com/

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps