Leakage currents & mismatch

M

mm77

Guest
Hi all,
is there a way to simulate the effect of mismatch in parasitics (in
particular parasitic diodes)?
The pn junction of n-wells for PMOS are not in the schematic.
1) How could I get them from the extracted view?
2) How could I simulate the mismatch in those?
Thanks,
marco
 
Hi Marco,

The parasitic diodes are extracted if you PDK RCX file is capable of
this. In other words, your Calibre/Assura rule files should implement
this built-in parasitic diode as a proper device to be extracted along
with 'wanted' devices. That said, I don't recall having seen such a
feature - Nwell to Psubstrate diode - in any of the PDKs I have used
before. The parasitic diodes I used to work with are those involved in
triple well process: Deep Nwell to Pwell diodes + Deep Nwell to
Psubstrate diodes. This is slightly different from what you are
talking about.

In what concerns the mismatch, I'm not sure I have got your question.
Assuming I have understood, I would rather say that there is no
mismatch that should be accounted with parasitics. In fact, we usually
simulate mismatch for MOS devices because of the fluctuation of th Vt,
mobility and the gate oxcyde. Similarly, mismatch in resistors is
primarily due to fluctuations in the sheet resistance and other
parameters that depend on the nature of a resistor: Poly, diffusion.
Again, the thin oxcyde in MIM capacitors is the main reason behind
mismatch. Parasitics are simply metal wires and as far as the physics
are concerned, I don't know of any parameter that makes a wire
different from another. Well, in modern technology nodes, people are
talking about lithography and copper CMP that impacts parasitics. As
far as I understand, this rather fall under the DFM flow rather than
the mismatch. For me, the RC parasitics are still to be considered as
ideal and without any mismatch.

Hope this helps :)

Riad.
 
On 3 Feb, 00:02, Riad KACED <riad.ka...@gmail.com> wrote:
Hi Marco,

The parasitic diodes are extracted if you PDK RCX file is capable of
this. In other words, your Calibre/Assura rule files should implement
this built-in parasitic diode as a proper device to be extracted along
with 'wanted' devices. That said, I don't recall having seen such a
feature - Nwell to Psubstrate diode - in any of the PDKs I have used
before. The parasitic diodes I used to work with are those involved in
triple well process: Deep Nwell to Pwell diodes + Deep Nwell to
Psubstrate diodes. This is slightly different from what you are
talking about.
Click to expand...
The process in question has no triple well, and it does extract
parasitc diodes.
One problem I have is that from the extracted view it's not so easy to
reconstruct the connectivity, because the net names are different
(except I think terminals names).

In what concerns the mismatch, I'm not sure I have got your question.
Assuming I have understood, I would rather say that there is no
mismatch that should be accounted with parasitics. In fact, we usually
simulate mismatch for MOS devices because of the fluctuation of th Vt,
mobility and the gate oxcyde. Similarly, mismatch in resistors is
primarily due to fluctuations in the sheet resistance and other
parameters that depend on the nature of a resistor: Poly, diffusion.
Again, the thin oxcyde in MIM capacitors is the main reason behind
mismatch. Parasitics are simply metal wires and as far as the physics
are concerned, I don't know of any parameter that makes a wire
different from another. Well, in modern technology nodes, people are
talking about lithography and copper CMP that impacts parasitics. As
far as I understand, this rather fall under the DFM flow rather than
the mismatch. For me, the RC parasitics are still to be considered as
ideal and without any mismatch.
Click to expand...
No, in this particular case I really need to simulate the mismatch of
leakage currents in those parasitic diodes (junctions), due to
mismatch in the size of the corresponding MOS.
Any hints?

I thought that maybe dcmatch analisys could do the job, but I don't
know how to add those diodes to the mismatch contributors (I think
I'll have to do it manually, but don't know how).

Marco
 
Hi Marco,

My understanding of your problem is getting worse I'm afraid. Anyway,
Spectre DCMATCH analysis is available for BJT, BSIM3v3, BSIM4,
BSIMSOI, BSIM5, EKV, VBIC, resistor and resistor-type bsource. That's
what you could see from the doc (spectre -h dcmatch). There is no
support for diodes at all.
I'm pretty much sure you have good reasons in chasing after parasitic
diode mismatch whereas you allow yourself a mismatch in the MOS
transistors.
What you are aiming for is still unclear to me; I can't make any
suggestion therefore :-(

Riad.
 
On 3 Feb., 00:30, mm77 <marcoball...@gmail.com> wrote:

No, in this particular case I really need to simulate the mismatch of
leakage currents in those parasitic diodes (junctions), due to
mismatch in the size of the corresponding MOS.
Any hints?

I thought that maybe dcmatch analisys could do the job, but I don't
know how to add those diodes to the mismatch contributors (I think
I'll have to do it manually, but don't know how).

Marco
Click to expand...
Hi Marco,
as RIAD wrote: "Spectre DCMATCH analysis is available for BJT ..."
could you possibly use the BJT model for your parasitic diodes?
Yes, manually of course :-( Just an idea, really don't know if
feasible.
erikl
 
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