[Layuot] Why more fingers less parasitic capacitance?

[boki]

Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Share dran/source?


Thanks.

Boki.

 

[Paul Burridge]

On 29 Apr 2004 23:04:45 -0700, bokiteam@ms21.hinet.net (boki) wrote:

Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Maybe your fingers are in series. Most people have parallel fingers.
--

The BBC: licenced at public expense to spread lies.

 

[Jim Thompson]

On 29 Apr 2004 23:04:45 -0700, bokiteam@ms21.hinet.net (boki) wrote:

Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Share dran/source?


Thanks.

Boki.

Draw the layout for both cases and then you will see. You'll need
spacing rules so that you can do the layout properly. I assume you
are in a university where this information should be available.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[boki]

Paul Burridge <pb@notthisbit.osiris1.co.uk> wrote in message news:<ith490hr13ti80vlf7ca360nce3hrqr0i0@4ax.com>...

On 29 Apr 2004 23:04:45 -0700, bokiteam@ms21.hinet.net (boki) wrote:

Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Maybe your fingers are in series. Most people have parallel fingers.

Of course parallel @@...

 

[boki]

Paul Burridge <pb@notthisbit.osiris1.co.uk> wrote in message news:<ith490hr13ti80vlf7ca360nce3hrqr0i0@4ax.com>...

On 29 Apr 2004 23:04:45 -0700, bokiteam@ms21.hinet.net (boki) wrote:

Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Maybe your fingers are in series. Most people have parallel fingers.

Of course parallel @@...

 

[Boki]

Thank you, of course, we have design rules, I had tape out several times.

I designed several type of 1-V Switched-Capacitor Switched-Opamp
Sigma-Delta Modulator,

I need mos/cmos to be switch, so, the parasitic capacitance is a big problem
to input signal,

My conclusion, if chip area is available, minimum width of mos with maximum
fingers will be the best switch, and the NMOSMOS ratio is 1:4

Q: The fingers decrease the parasitic capacitance, becasues shrare source
and drain?


Thanks for every reply.

Best regards,

Boki.




"Jim Thompson" <thegreatone@example.com> ???
news:0et4901h5qb10kot3qnai3mvt8mc0d9c6s@4ax.com ???...

On 29 Apr 2004 23:04:45 -0700, bokiteam@ms21.hinet.net (boki) wrote:

Dear All,

In CMOS layout, why more mos fingers we get less parasitic capacitance?

Share dran/source?


Thanks.

Boki.

Draw the layout for both cases and then you will see. You'll need
spacing rules so that you can do the layout properly. I assume you
are in a university where this information should be available.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.