layout

[mariam_telnet]

hi
i want to know the steps to make a layout of inductor??
tank you

 

[JD]

Hi,

Many technologies have build-in pcells for the inductors, it will save
you tons of time, and it has build-in model for that too. It means you
don't need to model the inductor by yourself.

If your process technology don't have inductor pcell, you can layout
it by some other tools and imported it to Cadence. ASITIC is one of
the good free tools you may want have a try.

It can layout the inductor and create a PI model for that inductor.

You can also choose to layout in Virtosu by hand, it need quite bit of
work, and you still need to port it the third party tools to model it.

JD

On Oct 15, 3:26 am, mariam_telnet <MARIAM.BOUGHAR...@gmail.com> wrote:

hi
i want to know the steps to make a layout of inductor??
tank you

 

[John Gianni]

I've posted this template for a 1-hour RTL-to-GDSII custom-IC
flow before; but here it is again for your edification.

If you wish, you can build digital blocks OUTSIDE the
standard Cadence digital flow (you can also floorplan, route,
chip finish, and verify absolutely huge designs in the Cadence
custom-IC flow, but, this newsgroup post concerns only the
creation of small digital blocks).

In one hour, you should be able to easily lay out a DRC/LVS-correct
block about the size of, say, an 8-bit up-down-counter (or thereabouts),
using only Cadence custom-IC solutions, starting from an RTL
gate-level netlist (it's just more than 1 hour for larger blocks).

Basically, the custom-IC RTL-to-GDSII automated flow is:
a) Assuming you have a gate-level netlist (if you are starting with
Verilog RTL not yet mapped to gates, then just add a quick
synthesis step); a process design kit; & a standard cell library ...

b) Start up Cadence Design Framework II & import your Verilog RTL using:
CIW: File->Import->Verilog
This will read in your gate-level Verilog to create a gate-level schematic.
In the latest DFII software, you can also bring in a transistor-level
netlist of each of the standard-cell blocks to create an editable
transistor-level schematic of every standard-cell block, using:
CIW: File->Import->CDL
This quickly provides you a complete editable simulatable hierarchical
block-level & transistor-level schematic of your entire design.

c) Simulate your design providing a test bench to wiggle the inputs and
outputs as you see fit. Use Cadence Virtuoso Composer for the schematic
environment; and use, for example, AMS Designer, NC-Sim, UltraSim,
or Spectre (all provided by Cadence) as your simulator.

Or use any simulator of choice (almost all have already been bolted
into Cadence Design Framework II using the APIs provided by Cadence).

d) Once your design simulates nicely, generate layout from the schematic.
There are many ways to do this; so I'll just suggest for this posting:
COMPOSER: Tools->Design Synthesis->Layout XL

This will bring up the Virtuoso layout environment.

Now press, in the Virtuoso layout environment:
LAYOUT: Design->Gen from Source

This will quickly create a brand new layout with all standard cells
(& transistors) approximately in the same location on the new layout
as in the original schematic.

At this point, you can manually or automatically place these blocks
and/or transistors in the location you desire.

If you wish to automatically place the standard cells and/or transistors,
bring up the Virtuoso Custom Placer using:
LAYOUT: Place->Placer

e) Once you have the standard cells and/or transistors placed, route between
those standard cells and/or transistors using the Virtuoso Custom Router:
LAYOUT: Route->Perform Route

f) Once you've routed you can compact the results using:
LAYOUT: Compact->Compact
(or you can just skip the compaction step if you so desire).

g) The now placed & routed results should be DRC/LVS correct; but, you'll
generally wish to run a physical verification tool to be sure:
LAYOUT: Verify->DRC
LAYOUT: Verify->LVS

h) If desired, extract the design, using Assura RCX for example, to obtain
a new layout, with parasitics - which you can re-simulate and compare
results with the original schematic (the parastics will be overlaid upon
the original schematic to allow cross probing with waveforms & layout).

i) Once your are sure your new design is running well, output to a EDA
industry compatible formats, e.g., GDSII, OpenAccess, LEF, .TLF,
or whatever:
CIW: File->Export->Stream (to output industry standard GDSII)
CIW: Tools->Abstract Generator (to output industry standard LEF)
CIW: Tools->Aptivia (to output industry standard TLF, .LIB)
csh% cdb2oa (to output industry standard OpenAccess)
etc.

Here is the original RTL which was tested in this one-hour custom flow:
// up_down.v
// 04/28/02

`timescale 1ps / 1ps
`define width 8

/////////////////////////////////////////////
module up_down (q, clk, d, dec, inc, load);

output [`width - 1:0] q;
input clk;
input [`width - 1:0] d;
input dec, inc, load;

wire [`width - 1:0] d;
reg [`width - 1:0] q;

always @(posedge clk)
begin
if (inc)
q = q + 1;
else if (dec)
q = q - 1;
else if (load)
q = d;
else
q = q;
end

endmodule

Here is the Verilog Gates netlist quickly synthesized (in a minute)
and tested with this one-hour custom flow to build digital blocks:

// Generated by automatic means on Mon Apr 29 21:19:53 PST 2002.
module AWACL_UNS_DEC_8_C(A, Z);
input [7:0] A;
output [7:0] Z;

NOR2X1 i_122(.A(A[3]), .B(A[4]), .Y(n_1163));
AOI31X1 i_270(.A0(n_12217), .A1(A[7]), .A2(n_12225), .B0(n_131), .Y(Z[7]
));
AOI21X1 i_8(.A0(n_12217), .A1(n_12225), .B0(A[7]), .Y(n_131));
NOR4X1 i_131(.A(A[2]), .B(A[3]), .C(A[1]), .D(A[0]), .Y(n_1169));
AOI31X1 i_269(.A0(n_122), .A1(A[6]), .A2(n_12223), .B0(n_136), .Y(Z[6])
);
AOI21X1 i_13(.A0(n_122), .A1(n_12223), .B0(A[6]), .Y(n_136));
NOR4BX1 i_134(.AN(n_1163), .B(A[1]), .C(A[2]), .D(A[0]), .Y(n_11611));
AOI21X1 i_268(.A0(n_11611), .A1(A[5]), .B0(n_151), .Y(Z[5]));
NOR2X1 i_18(.A(n_11611), .B(A[5]), .Y(n_151));
AOI21X1 i_267(.A0(A[4]), .A1(n_1169), .B0(n_159), .Y(Z[4]));
NOR2X1 i_23(.A(n_1169), .B(A[4]), .Y(n_159));
NOR2X1 i_4(.A(A[0]), .B(A[1]), .Y(n_122));
AOI21X1 i_266(.A0(n_12217), .A1(A[3]), .B0(n_164), .Y(Z[3]));
NOR2X1 i_28(.A(n_12217), .B(A[3]), .Y(n_164));
NOR3X1 i_445(.A(A[1]), .B(A[2]), .C(A[0]), .Y(n_12217));
AOI21X1 i_265(.A0(n_122), .A1(A[2]), .B0(n_170), .Y(Z[2]));
NOR2X1 i_33(.A(n_122), .B(A[2]), .Y(n_170));
XNOR2X1 i_264(.A(A[0]), .B(A[1]), .Y(Z[1]));
NOR4X1 i_454(.A(A[2]), .B(A[3]), .C(A[4]), .D(A[5]), .Y(n_12223));
NOR4X1 i_457(.A(A[3]), .B(A[4]), .C(A[5]), .D(A[6]), .Y(n_12225));
INVX1 i_62(.A(A[0]), .Y(Z[0]));
endmodule
module AWACL_UNS_INC_8_C(A, Z);
input [7:0] A;
output [7:0] Z;

NAND4X1 i_84(.A(A[3]), .B(A[4]), .C(A[5]), .D(A[6]), .Y(n_64));
AOI21X1 i_112(.A0(n_18130), .A1(A[7]), .B0(n_196), .Y(Z[7]));
NOR2X1 i_1(.A(n_18130), .B(A[7]), .Y(n_196));
NAND4X1 i_83(.A(A[2]), .B(A[3]), .C(A[4]), .D(A[5]), .Y(n_62));
AOI21X1 i_111(.A0(n_18128), .A1(A[6]), .B0(n_201), .Y(Z[6]));
NOR2X1 i_6(.A(n_18128), .B(A[6]), .Y(n_201));
NAND2X1 i_73(.A(A[3]), .B(A[4]), .Y(n_37));
XNOR2X1 i_110(.A(n_18126), .B(A[5]), .Y(Z[5]));
XNOR2X1 i_109(.A(n_18732), .B(A[4]), .Y(Z[4]));
NAND2X1 i_63(.A(A[0]), .B(A[1]), .Y(n_181));
INVX1 i_64(.A(n_181), .Y(n_182));
NAND4BXL i_6359(.AN(n_37), .B(A[1]), .C(A[2]), .D(A[0]), .Y(n_18126));
XNOR2X1 i_108(.A(n_187), .B(A[3]), .Y(Z[3]));
NOR2X1 i_6362(.A(n_181), .B(n_62), .Y(n_18128));
AOI31X1 i_107(.A0(A[0]), .A1(A[1]), .A2(A[2]), .B0(n_221), .Y(Z[2]));
NOR2X1 i_26(.A(n_182), .B(A[2]), .Y(n_221));
NOR2X1 i_6365(.A(n_187), .B(n_64), .Y(n_18130));
NAND3X1 i_66(.A(A[1]), .B(A[2]), .C(A[0]), .Y(n_187));
AOI21X1 i_106(.A0(A[0]), .A1(A[1]), .B0(n_226), .Y(Z[1]));
NOR2X1 i_31(.A(A[0]), .B(A[1]), .Y(n_226));
NAND3X1 i_6668(.A(A[2]), .B(A[3]), .C(n_182), .Y(n_18732));
INVX1 i_57(.A(A[0]), .Y(Z[0]));
endmodule
module up_down(q, clk, d, dec, inc, load);

output [7:0] q;
input clk;
input [7:0] d;
input dec;
input inc;
input load;

wire [7:0] nbus_3;
wire [7:0] nbus_0;

OAI2BB1X1 i_0(.A0N(q[7]), .A1N(n_96), .B0(n_100), .Y(n_59));
OAI2BB1X1 i_1(.A0N(q[6]), .A1N(n_96), .B0(n_102), .Y(n_64));
OAI2BB1X1 i_2(.A0N(q[5]), .A1N(n_96), .B0(n_104), .Y(n_69));
OAI2BB1X1 i_3(.A0N(q[4]), .A1N(n_96), .B0(n_106), .Y(n_74));
OAI2BB1X1 i_4(.A0N(q[3]), .A1N(n_96), .B0(n_108), .Y(n_79));
OAI2BB1X1 i_5(.A0N(q[2]), .A1N(n_96), .B0(n_110), .Y(n_84));
OAI2BB1X1 i_6(.A0N(q[1]), .A1N(n_96), .B0(n_112), .Y(n_89));
OAI2BB1X1 i_7(.A0N(q[0]), .A1N(n_96), .B0(n_114), .Y(n_94));
NOR2X1 i_8(.A(dec), .B(inc), .Y(n_95));
NOR3X1 i_11(.A(dec), .B(inc), .C(load), .Y(n_96));
AND2X1 i_10(.A(load), .B(n_95), .Y(n_97));
NOR2BX1 i_9(.AN(dec), .B(inc), .Y(n_98));
AOI222X1 i_17(.A0(nbus_3[7]), .A1(n_98), .B0(inc), .B1(nbus_0[7]), .C0(d
[7]), .C1(n_97), .Y(n_100));
AOI222X1 i_24(.A0(n_98), .A1(nbus_3[6]), .B0(inc), .B1(nbus_0[6]), .C0(
n_97), .C1(d[6]), .Y(n_102));
AOI222X1 i_31(.A0(n_98), .A1(nbus_3[5]), .B0(inc), .B1(nbus_0[5]), .C0(
n_97), .C1(d[5]), .Y(n_104));
AOI222X1 i_38(.A0(n_98), .A1(nbus_3[4]), .B0(inc), .B1(nbus_0[4]), .C0(
n_97), .C1(d[4]), .Y(n_106));
DFFHQX1 q_reg_0(.D(n_94), .CK(clk), .Q(q[0]));
DFFHQX1 q_reg_1(.D(n_89), .CK(clk), .Q(q[1]));
AOI222X1 i_45(.A0(n_98), .A1(nbus_3[3]), .B0(inc), .B1(nbus_0[3]), .C0(
n_97), .C1(d[3]), .Y(n_108));
DFFHQX1 q_reg_2(.D(n_84), .CK(clk), .Q(q[2]));
DFFHQX1 q_reg_3(.D(n_79), .CK(clk), .Q(q[3]));
AOI222X1 i_52(.A0(n_98), .A1(nbus_3[2]), .B0(inc), .B1(nbus_0[2]), .C0(
n_97), .C1(d[2]), .Y(n_110));
DFFHQX1 q_reg_4(.D(n_74), .CK(clk), .Q(q[4]));
DFFHQX1 q_reg_5(.D(n_69), .CK(clk), .Q(q[5]));
AOI222X1 i_59(.A0(n_98), .A1(nbus_3[1]), .B0(inc), .B1(nbus_0[1]), .C0(
n_97), .C1(d[1]), .Y(n_112));
DFFHQX1 q_reg_6(.D(n_64), .CK(clk), .Q(q[6]));
DFFHQX1 q_reg_7(.D(n_59), .CK(clk), .Q(q[7]));
AOI222X1 i_66(.A0(nbus_3[0]), .A1(n_98), .B0(inc), .B1(nbus_0[0]), .C0(d
[0]), .C1(n_97), .Y(n_114));
AWACL_UNS_DEC_8_C i_166(.A(q), .Z(nbus_3));
AWACL_UNS_INC_8_C i_82(.A(q), .Z(nbus_0));
endmodule

In summary, I've seen blocks about the complexity of the 8-bit up/down
counter above synthesized, imported, simulated, placed, routed, verified,
extracted, & re-simulated in an hour or less. You can, of course, handle
larger blocks; it will just take longer than an hour from start to finish.

--
JOHN_GIANNI
This is a personal opinion not specifically sanctioned by my employer or my ISP.
I do NOT read email at this nom d' Internet; it is merely a spam trap.
Comments, corrections, commendations, complaints should go to the NG.