Layout querry

M

meghna

Guest
Hi,
I am using Vituoso tool for custom layout.
As I heard that it is not safe to give single contact as it may create the
problem (say there may be no connection) at fabrication stage. Is it really
so, means is it necessary to give more than one contact?
Thanks!
 
If current is not your concern, then I've heard different things. Some
say that some manufacturing process technologies are really reliable,
and that you really don't need more than one contact or via for most
cases. But many people would say that from a process point of view, if
you can fit a double contact in, go ahead and put it in, especially if
the contact or via is in a cell that is repeated many times in your
layout. If you have a double contact then if one of the contact was not
thoroughly etched, you still have one reliable contact left, thus your
wafer will "yield" more good chips. So, you probably should, check
with your circuit engineer for guidance, they stay up to date on all
that type of information.
 
If it will answer your question i read somewhere that for memory layout
double contacts are necessary




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meghna wrote:
As I heard that it is not safe to give single contact as it may
create the
problem (say there may be no connection) at fabrication stage. Is it
really
so, means is it necessary to give more than one contact?
Click to expand...
It depends on the process.

There are current mainstream high-volume foundry processes
that highly recommend:

- double via if you can

- single via with non-minimum enclosure if you cannot

- single minimum-enclosure via as a last resort

For the processes I'm talking about, this is extremely well
documented in the design rules, and is for the sake of improving
yield. If the design rules for your process do not call out
any such requirements, don't worry about it.

In addition, all(?) modern copper metal processes have mandatory
rules that require multiple vias where one of the metal features
is "wide" (for some definition of "wide" and "multiple").
This is *NOT* just a yield enhancement, and again, the design
rule documents are very explicit about it. I don't think this
is what you're worrying about, though.

-Jay-
 
Read the other posts.
Statistically the chance of a failed via is low, might be 1e-6 (more
likely to get high R and blow timing). That looks pretty low does it not
1 in a million.

If your chip has 1e6 single vias you get good odds of a failure
= (1-1e-6)^(1e6) = 0.3678 probability of no failure given independent
odds.

Using double vias this is (damn calculator can't do the math).
(1-1e-12)^1e6 =


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I think the larger problem is not with "open" contacts which
are somewhat unlikely, but with marginal ones.

If your circuit requires a very low impedance contact/via, then the
circuit will benefit from a double contact/via structures.

This has more to do with the non-clustered behaviour of the marginal
contacts. Note that it is not too unlikely to get a contact/via that is
10x the impedance of the nominal one, but it is extremely unlikely
to get two of them close together.

When your path is non-critical for speed, and density is paramount,
then go with single structures. When the signal is critical (especially
a current sensitive one) then go with more!

Note that any reliability discussion should really be taken up with your Fab
and all of the reliability and yield issues can change with new processing.

YMMV

-- Gerry www.ictooling.com


"meghna" <meghna@protected_id> wrote in message
news:c3599a73902c164a2dcf126adac04000@localhost.talkaboutcad.com...
Hi,
I am using Vituoso tool for custom layout.
As I heard that it is not safe to give single contact as it may create the
problem (say there may be no connection) at fabrication stage. Is it
really
so, means is it necessary to give more than one contact?
Thanks!
Click to expand...
 
Thanks for all your replies. I have one more querry regarding layouts. Poly
lines are generally taken as vertical (as I have seen in most of the
layouts). Is there any specific advantage of that? I know one of the
advantage related to gate shadowing effect. Does it really matters?

Regards
 
No!

Typically the Metal1 lines were drawn horizontal.

This makes it more natural to draw the Poly vertical.

Standard cells typically have the gates vertical.

This also makes it easier to route poly vertical.

Poly is somewhat High Rho (as compared to metals) so long runs
are usually problematic. Poly is typically used to "Stub out" connection
into cells.

"meghna" <meghna@protected_id> wrote in message
news:82f85ce165b95333b4b147b2d2490a61@localhost.talkaboutcad.com...
Thanks for all your replies. I have one more querry regarding layouts.
Poly
lines are generally taken as vertical (as I have seen in most of the
layouts). Is there any specific advantage of that? I know one of the
advantage related to gate shadowing effect. Does it really matters?

Regards
Click to expand...
 
Actually, a particular fabrication process may be optimized for vertical
poly lines. It's easier to guarantee good poly connectivity, CD (critical
dimension) variation, reliability, etc. if the fab settings (particularly
the optical lithography/illumination settings) can be optimized for a
single gate orientation. Check with your fab to see if this is the case.

Frank


On Wed, 09 Mar 2005 14:18:12 -0500, G Vandevalk wrote:

No!

Typically the Metal1 lines were drawn horizontal.

This makes it more natural to draw the Poly vertical.

Standard cells typically have the gates vertical.

This also makes it easier to route poly vertical.

Poly is somewhat High Rho (as compared to metals) so long runs
are usually problematic. Poly is typically used to "Stub out" connection
into cells.

"meghna" <meghna@protected_id> wrote in message
news:82f85ce165b95333b4b147b2d2490a61@localhost.talkaboutcad.com...
Thanks for all your replies. I have one more querry regarding layouts.
Poly
lines are generally taken as vertical (as I have seen in most of the
layouts). Is there any specific advantage of that? I know one of the
advantage related to gate shadowing effect. Does it really matters?

Regards
Click to expand...
 
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