Layout Extraction

[David Varghese]

Hello,

I am doing the layout of a schematic in Cadence that has vdda!, vssa!
and gnda! terminals. While checking the nets connected in the
extracted view of the cell it was observed that the drain and the
source terminals of the nmos and pmos transistors are are not
identified exactly as expected and hence the connections have been
mixed up. So I am kinda stuck to find out what exactly would be the
cause for this
problem. Looks like the extraction routine does not identify the right
potentials
in the layout with vdda!, vssa! and gnda!.I suspect whether it has go
to do anything with the design rules file. It might not have
information regarding these terminals(vdda!,gnda!,vssa!), because I
dont observe a similar problem when I tried out extracting layouts of
other circuits which has just vdd and gnd. Has anybody come across a
similar problem and has managed to troubleshoot it? Would be great if
someone could
help me in this matter.

Regards,

David

 

[Edward J Kalenda]

How do you expect the device recognition routines to determine source
and drain? There is no layout difference.

On 20 Nov 2003 11:59:21 -0800, dvarghes@soton.ac.uk (David Varghese)
wrote:

Hello,

I am doing the layout of a schematic in Cadence that has vdda!, vssa!
and gnda! terminals. While checking the nets connected in the
extracted view of the cell it was observed that the drain and the
source terminals of the nmos and pmos transistors are are not
identified exactly as expected and hence the connections have been
mixed up. So I am kinda stuck to find out what exactly would be the
cause for this
problem. Looks like the extraction routine does not identify the right
potentials
in the layout with vdda!, vssa! and gnda!.I suspect whether it has go
to do anything with the design rules file. It might not have
information regarding these terminals(vdda!,gnda!,vssa!), because I
dont observe a similar problem when I tried out extracting layouts of
other circuits which has just vdd and gnd. Has anybody come across a
similar problem and has managed to troubleshoot it? Would be great if
someone could
help me in this matter.

Regards,

David

 

[S. Badel]

the extraction does not identify net names such
as vdda! or vssa! or whatever, exept if you
explicitely assign a name to a node by labelling
it, and provided the tech files contains the code
for doing it.
remember the schematic and layout are not the
same, they are designed separatedly and the
connection between them is made through
lvs. even if the net names are different in
the extracted view and in the schematic, lvs will
match them and report any errors.

this is where the source and drain may be
identified, that is, they are the same but
the way they are connected to the rest
of the circuit is different. in any other
respect extractor or lvs don't care a nut
about source and drain (you shouldn't either
calling one terminal source and the other
drain makes sense only in particular
situations, where one is at a
potential higher that the other.

i suggest you run lvs and maybe discover
errors in your layout. if you want to have
specific net names in the extracted view
use labels.

stephane

"David Varghese" <dvarghes@soton.ac.uk> wrote in message
news:366fb57d.0311201159.605390ad@posting.google.com...

Hello,

I am doing the layout of a schematic in Cadence that has vdda!, vssa!
and gnda! terminals. While checking the nets connected in the
extracted view of the cell it was observed that the drain and the
source terminals of the nmos and pmos transistors are are not
identified exactly as expected and hence the connections have been
mixed up. So I am kinda stuck to find out what exactly would be the
cause for this
problem. Looks like the extraction routine does not identify the right
potentials
in the layout with vdda!, vssa! and gnda!.I suspect whether it has go
to do anything with the design rules file. It might not have
information regarding these terminals(vdda!,gnda!,vssa!), because I
dont observe a similar problem when I tried out extracting layouts of
other circuits which has just vdd and gnd. Has anybody come across a
similar problem and has managed to troubleshoot it? Would be great if
someone could
help me in this matter.

Regards,

David