Lattice Mico32 Simulation in Modelsim

Hi,

I have written a Mico32 application in C.

Now I want to simulate my Mico32 system in the Modelsim simulator including the C application (toggling some LEDs, ISR for controling 7 SEGMENT display).
As I have found out (by reading the Mico32 HW/SW handbook) I can create a memory initialization file which is 148MByte after generation. For that I have used
the Mico32 Software Deployment Tools -> Mico32 On Chip Memory Deployment.

My quesiton: What do I have to do next to simulate it in Modelsim? The Mico32 handbooks are not very helpful concerning that point.


Thanks, Noro

 

Is 148MB the size of the final contents of the on chip memory? If so, you may be doing something very wrong; I don't think I know of any FPGA has on chip memory anywhere near that large! C code for toggling LEDs and such should not compile to such a huge file.

To simulate it, you should just need a test bench in your chosen HDL that asserts all the inputs and hooks up all the outputs so you can see them plotted.

In principle, if your vendor has hooked everything up right, then the pre-synthesis simulation should already be accounting for the program code sitting in your on-chip memory. Be sure to generate all the clocks and reset signals, if everything doesn't get a reset in the beginning of sim, modelsim tends to leave signals in an indeterminate state rather than assuming they should start at some default values.

On Friday, August 12, 2016 at 6:58:24 AM UTC-7, noreeli...@gmail.com wrote:

Hi,

I have written a Mico32 application in C.

Now I want to simulate my Mico32 system in the Modelsim simulator including the C application (toggling some LEDs, ISR for controling 7 SEGMENT display).
As I have found out (by reading the Mico32 HW/SW handbook) I can create a memory initialization file which is 148MByte after generation. For that I have used
the Mico32 Software Deployment Tools -> Mico32 On Chip Memory Deployment.

My quesiton: What do I have to do next to simulate it in Modelsim? The Mico32 handbooks are not very helpful concerning that point.


Thanks, Noro

 

>To simulate it, you should just need a test bench in your chosen HDL that >asserts all the inputs and hooks up all the outputs so you can see them plotted.

But how do I get the C program sequence into my HDL design (FPGA embedded memory blocks) for functional simulation if the generated memory ini file is shooting FPGA ressources?

 

Additional point:
The .elf file which is used to generate the memory ini file has 100 KB.

 

[rickman]

On 8/16/2016 6:09 AM, noreeli.schmidt@gmail.com wrote:

To simulate it, you should just need a test bench in your chosen HDL that >asserts all the inputs and hooks up all the outputs so you can see them plotted.

But how do I get the C program sequence into my HDL design (FPGA embedded memory blocks) for functional simulation if the generated memory ini file is shooting FPGA ressources?

It is very likely that if you wish to simulate such a large program that
it won't fit on FPGA resources, it may not be practical to run in the
HDL simulator. Keep in mind the simulation will run many orders of
magnitude slower than real time.

--

Rick C