Lattice ISPLever - how to prevent inferred latch

[Mike Harrison]

I noticed an odd thing happenning with Lattice EC VHDL project....

I have a register config1(7 downto 0) holding various configuration states, updated in a state
machine which only gets clocked at certain times (i.e. not continuous).

All bits of this register are set to 0 on powerup (implicitly, as per VHDL default).

I then assign a couple of pins to output a bit in this register for debug purposes

pin112<= not config1(5);
pin109<= config1(5);

However on powerup, both of these pins are low. When the config1 register is subsequently clocked,
the pins then reflect the true and inverted states as you'd expect.

The compile report does appear to suggest it is inferring latches for these signals.

TN1008 suggests use of else to avoid inferred latches, so I also tried

pin112<='0' when config1(5)='1' else '1';

with the same result - it is still inferring a latch.

I've worked around this by explicitly latching the signals from a continuous clock, but how would
I force it to NOT infer the latch, and use a simple combinatorial inverter from the register to the
pin?

 

[rickman]

On Dec 29, 1:00 pm, Mike Harrison <m...@whitewing.co.uk> wrote:

I noticed an odd thing happenning with Lattice EC VHDL project....

I have  a register config1(7 downto 0) holding various configuration states, updated in a state
machine which only gets clocked at certain times (i.e. not continuous).

All bits of this register are set to 0  on powerup (implicitly, as per VHDL default).

I then assign a couple of pins to output a bit in this register for debug purposes

pin112<= not config1(5);
pin109<= config1(5);

However on powerup, both of these pins are low. When the config1 register is subsequently clocked,
the pins then reflect the true and inverted states as you'd expect.

The compile report does appear to suggest it is inferring latches for these signals.

TN1008 suggests use of else to avoid inferred latches, so I also tried

pin112<='0' when config1(5)='1' else '1';

with the same result - it is still inferring a latch.

I've worked around this by explicitly  latching the signals from  a continuous clock, but how would
I force it to NOT infer the latch, and use a simple combinatorial inverter from the register to the
pin?

If you are making the assignment to config1 in a clocked process I
expect you are omitting an explicit reset assignment. I'm not sure
what logic is generated under these conditions, or why, but I always
include an assignment to registers for the reset state.

The only way I can think that the two outputs would be in the states
you describe is if the register is being replicated and pushed into
the IOBs. Each of the FFs might be reset by the power on reset,
assuming a correct value after being clocked.

When you say your state machine is not clocked continuously, do you
mean you are gating the clock? Or are you enabling the clock? You
might want to simplify your code to a test case and if the problem
remains, post it here. If the problem goes away try adding in more of
the actual code until it breaks.

Otherwise, maybe you could post your code for us to read.

Rick