latency problem

may you all be happy, and live a peaceful life. i have a problem. i
will be grateful for any sort of help

i have a parent module calling various child modules. all the modules
are synchronised by a single clock. however the first module gives the
output at the first edge of clock, the next at second edge and so on.
this brings a latency of about 5 clock cycles in my system how can i
get rid of this latency?

 

[Per]

On 2008-12-03, m.umar.kk@gmail.com <m.umar.kk@gmail.com> wrote:

may you all be happy, and live a peaceful life. i have a problem. i
will be grateful for any sort of help

i have a parent module calling various child modules. all the modules
are synchronised by a single clock. however the first module gives the
output at the first edge of clock, the next at second edge and so on.
this brings a latency of about 5 clock cycles in my system how can i
get rid of this latency?

It sounds like you have FFs in the modules to pipeline the
computation. The only way you can get rid of the latency would be
to use pure combinatorial logic in your submodules. But then you
might run into timing problems. It all depends on your design.

\Per

 

[Mike Treseler]

m.umar.kk@gmail.com wrote:

may you all be happy, and live a peaceful life. i have a problem. i
will be grateful for any sort of help

i have a parent module calling various child modules. all the modules
are synchronised by a single clock. however the first module gives the
output at the first edge of clock, the next at second edge and so on.
this brings a latency of about 5 clock cycles in my system how can i
get rid of this latency?

Latency happens when I cascade synchronous modules.
Sometimes 5 ticks is not too long to wait.
If it were, I would have to combine some of the modules.

However, when I check static timing on the combined module,
I might now find that Fmax < Fclk and
have to revert to the original design

-- Mike Treseler