Latency independent BFM coding

[apurv]

Hi Group members,

I have one interface where response data from DUT can come after N
clock cycles of asserting the read request. This N can be any value
depending upon the design.

However DUT is not providing any valid signal along with data.

If I am writing verilog BFM ( part of verification environment ) for
this interface. What I would write for single read request is something
like this

task single_rd;
begin
rd_req <= 1'b1;
@( posedge clk);
rd_req <= 1'b0;
repeat( N - 1)
@( posedge clk);
resp_data <= resp_data_on_bus;
end
endtask

One of the limitations of this code is that it is greatly dependent on
value of N. In real world where value of N ( read latency ) can change
frequently, this code loose the generality.

Can you suggest any other better way to do the same thing?

Thanks
apurv

 

[Alex]

I have one interface where response data from DUT can come after N
clock cycles of asserting the read request. This N can be any value
depending upon the design.

Looks like you must have an ACK signal in your protocol. It is unclear
how the protocol will work with the varying number of N.

-Alex

 

[apurv]

Hi Alex,

Basically there is no ack signal in protocol. The value of N is decided
by software. Once decided it remains fixed.

I am talking about the situation when the value is not fixed within
some duration say ( 1 to 3 )

At that time is there any way to code this thing in a better way?

Thanks
apurv

Alex wrote:

I have one interface where response data from DUT can come after N
clock cycles of asserting the read request. This N can be any value
depending upon the design.

Looks like you must have an ACK signal in your protocol. It is unclear
how the protocol will work with the varying number of N.

-Alex