latching AND gate

P

Pete

Guest
Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high remain
High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high input
when output goes high) strange things happen?

What am I doing wrong?
 
Pete wrote:
Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high remain
High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high input
when output goes high) strange things happen?

What am I doing wrong?
Click to expand...
You need more than one gate to perform the AND function and the ORing
of the output with one of the inputs to form a latch.

+---+
I1 ---| |
|AND|---+--- Output
+---| | |
| +---+ |
| +---+ |
| | |---+
+---|OR |
| |--- I2
+---+

Depending on the logic family, you may be able to get away with making
one of the gates with diodes.

--
John Popelish
 
Subject: latching AND gate
From: "Pete" pete@spam.no
Date: 4/12/2004 9:43 AM Central Standard Time
Message-id: <8Wxec.68033$Id.67995@news-binary.blueyonder.co.uk

Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high remain
High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high input
when output goes high) strange things happen?

What am I doing wrong?
Click to expand...
You're not doing anything wrong -- you need a latch circuit of some kind to go
with your AND gate.

However, if you've only got a CMOS AND gate, and you're willing to suffer the
embarassment of building a cheesy MML (Mickey Mouse Logic) circuit, try this
(view in fixed font or M$ Notepad):

Latching AND Gate (?!@$)
___ ___
I1 o--|___|--o---|___|--.
22K | 22K |
___ | __ |
I2 o--|___|--o---| | |
| 22K |& |---'
'-------------|__|

1/4 4081


Created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de (but not his
fault)

Remember this circuit will latch as you described, but it is slow, doesn't have
noise immunity, and biases the gate input in the linear region, which means it
will use a lot of power. BUT it might get you through. Just don't tell anyone
you got it from me.

Good luck
Not Chris
 
On Mon, 12 Apr 2004 11:52:34 -0400, John Popelish <jpopelish@rica.net>
wrote:

Pete wrote:

Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high remain
High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high input
when output goes high) strange things happen?

What am I doing wrong?

You need more than one gate to perform the AND function and the ORing
of the output with one of the inputs to form a latch.

+---+
I1 ---| |
|AND|---+--- Output
+---| | |
| +---+ |
| +---+ |
| | |---+
+---|OR |
| |--- I2
+---+
Click to expand...
---

+---+
I2 ---| |
|AND|---+--- Output
+---| | |
| +---+ |
| +---+ |
| | |---+
+---|OR |
| |--- I1
+---+

:)

--
John Fields
 
John Fields wrote:
On Mon, 12 Apr 2004 11:52:34 -0400, John Popelish <jpopelish@rica.net
wrote:

Pete wrote:

Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high remain
High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high input
when output goes high) strange things happen?

What am I doing wrong?

You need more than one gate to perform the AND function and the ORing
of the output with one of the inputs to form a latch.

+---+
I1 ---| |
|AND|---+--- Output
+---| | |
| +---+ |
| +---+ |
| | |---+
+---|OR |
| |--- I2
+---+

---

+---+
I2 ---| |
|AND|---+--- Output
+---| | |
| +---+ |
| +---+ |
| | |---+
+---|OR |
| |--- I1
+---+

:)

--
John Fields
Click to expand...
Thanks. I'll take all the help I can get. :)

--
John Popelish
 
"Pete" <pete@spam.no> wrote in message news:<8Wxec.68033$Id.67995@news-binary.blueyonder.co.uk>...
Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high remain
High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high input
when output goes high) strange things happen?

What am I doing wrong?
Click to expand...
Why not send the output to an OR gate along with I1 and feed that
to the AND gate in place of I1?
 
Sorry, did not see previous responses.

Why not send the output to an OR gate along with I1 and feed that
to the AND gate in place of I1?
Click to expand...
 
"Pete" <pete@spam.no> wrote in
news:8Wxec.68033$Id.67995@news-binary.blueyonder.co.uk:

Having problems controlling a AND gate that I want to latch.

Have two inputs I1 and I2

Output to go High when I1 and I2 are high, but once Output is high
remain High until I2 falls to low. (regardless of I1)

If I try to connect the output of the gate to I1 (to provide the high
input when output goes high) strange things happen?

What am I doing wrong?
Click to expand...
__
I2 O----------| \
| )--+--O Out
I1 O--|>|--+--|__/ |
| |
+---[R]---+

The source at the input I1 may be a factor in determining the size of
the resistor (but 10..100k will probably work).


--
Regards,
Soeren

* If it puzzles you dear... Reverse engineer *
 
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