latches

R

Runar Gjelsvik

Guest
When I design state-machines I always get a lot of latches. I don't know how
to get rid of these, I've tried my best in several different ways to make
the combinatorial process complete but without luck. I've go this state
machine here with all these warnings:

WARNING:Xst:737 - Found 2-bit latch for signal <address>.
WARNING:Xst:737 - Found 88-bit latch for signal <dataFrame>.
WARNING:Xst:737 - Found 2-bit latch for signal <prefix>.
WARNING:Xst:737 - Found 32-bit latch for signal <rcvData>.
WARNING:Xst:737 - Found 1-bit latch for signal <frameLoaded>.
WARNING:Xst:1291 - FF/Latch <rcvData_31> is unconnected in block
<data_sorter>.
WARNING:Xst:1291 - FF/Latch <rcvData_30> is unconnected in block
<data_sorter>.


load_data:Block

type STATE_TYPE is (IDLE, STORE, DISTRIB, RESET);

attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of STATE_TYPE: type is "0001 0010 0100 1000";

signal CS, NS: STATE_TYPE;
signal rcvData : std_logic_vector(31 downto 0);
signal prefix : unsigned(1 downto 0);
signal address : integer range 0 to 3;

begin

SYNC_PROC: process (clk, rst)
begin
if (rst='1') then
CS <= RESET;
elsif (clk'event and clk = '1') then
CS <= NS;
end if;
end process;

COMB_PROC: process (CS, loadData, dataIn, data(0), data(1), data(2),
prefix, rcvData)
begin
case CS is
when IDLE => if loadData = '1' then
frameLoaded <= '0';
rcvData <= dataIn;
prefix <= unsigned(dataIn(31 downto 30));
NS <= STORE;
end if;
when STORE =>
address <= to_integer(prefix);
case prefix is
when "00" => data(address) <= rcvData;
NS <= IDLE;
when "01" => data(address) <= rcvData;
NS <= IDLE;
when "10" => data(address) <= rcvData;
NS <= DISTRIB;
when others => NS <= RESET;
end case;

when DISTRIB =>
dataFrame <= (data(2)(27 downto 0) & data(1)(29 downto 0) & data(0)(29
downto 0));
frameLoaded <= '1';
NS <= IDLE;

when RESET => for i in 0 to 2 loop
data(i) <= (others => '0');
end loop;
dataFrame <= (others => '0');
rcvData <= (others => '0');
frameLoaded <= '0';
prefix <= (others => '0');
NS <= IDLE;
when others => NS <= RESET;
end case;
end process;
end block;
 
In the CASE statement you do not assign to address in all branches.
In state IDLE you do not assign to address; this means that the value of
address is remains its current value ==> your latch!

If you model a combinational circuit be sure to assign to a signal in all
branches.
In case the value of address is NOT important in the branches where do did
not assign to it you could consider assigning to address (and similar
signals) a value just before the case. Something like:

address <= "--"; -- any value is good
case CS is
...

Egbert Molenkamp

"Runar Gjelsvik" <runar.hates@spam.com> schreef in bericht
news:cfplv4$4ed$1@sunnews.cern.ch...
When I design state-machines I always get a lot of latches. I don't know
how
to get rid of these, I've tried my best in several different ways to make
the combinatorial process complete but without luck. I've go this state
machine here with all these warnings:

WARNING:Xst:737 - Found 2-bit latch for signal <address>.
WARNING:Xst:737 - Found 88-bit latch for signal <dataFrame>.
WARNING:Xst:737 - Found 2-bit latch for signal <prefix>.
WARNING:Xst:737 - Found 32-bit latch for signal <rcvData>.
WARNING:Xst:737 - Found 1-bit latch for signal <frameLoaded>.
WARNING:Xst:1291 - FF/Latch <rcvData_31> is unconnected in block
data_sorter>.
WARNING:Xst:1291 - FF/Latch <rcvData_30> is unconnected in block
data_sorter>.


load_data:Block

type STATE_TYPE is (IDLE, STORE, DISTRIB, RESET);

attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of STATE_TYPE: type is "0001 0010 0100 1000";

signal CS, NS: STATE_TYPE;
signal rcvData : std_logic_vector(31 downto 0);
signal prefix : unsigned(1 downto 0);
signal address : integer range 0 to 3;

begin

SYNC_PROC: process (clk, rst)
begin
if (rst='1') then
CS <= RESET;
elsif (clk'event and clk = '1') then
CS <= NS;
end if;
end process;

COMB_PROC: process (CS, loadData, dataIn, data(0), data(1), data(2),
prefix, rcvData)
begin
case CS is
when IDLE => if loadData = '1' then
frameLoaded <= '0';
rcvData <= dataIn;
prefix <= unsigned(dataIn(31 downto 30));
NS <= STORE;
end if;
when STORE =
address <= to_integer(prefix);
case prefix is
when "00" => data(address) <= rcvData;
NS <= IDLE;
when "01" => data(address) <= rcvData;
NS <= IDLE;
when "10" => data(address) <= rcvData;
NS <= DISTRIB;
when others => NS <= RESET;
end case;

when DISTRIB =
dataFrame <= (data(2)(27 downto 0) & data(1)(29 downto 0) &
data(0)(29
downto 0));
frameLoaded <= '1';
NS <= IDLE;

when RESET => for i in 0 to 2 loop
data(i) <= (others => '0');
end loop;
dataFrame <= (others => '0');
rcvData <= (others => '0');
frameLoaded <= '0';
prefix <= (others => '0');
NS <= IDLE;
when others => NS <= RESET;
end case;
end process;
end block;
Click to expand...
 
Runar Gjelsvik wrote:

When I design state-machines I always get a lot of latches. I don't know
how to get rid of these, I've tried my best in several different ways to
make the combinatorial process complete but without luck. I've go this
state machine here with all these warnings:
Click to expand...
Consider using a single synchronous process
for your controller.

-- Mike Treseler
 
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