Latch issue

R

rik

Guest
I have this following state machine. My question is though I have
default values for all the signals, why "req" and "dir" is inferred as
latches?


always@ (pres_st, bus_go, bus_write, wready, rready, timeout)
begin
// State Machine defaults
latch_data = 0;
ld_cmd = 0;
set_error = 0;
clr_error = 0;
set_done = 0;
clr_done = 0;
req = req;
dir = dir;
case (pres_st)

`IDLE_ST: if (bus_go)
begin
ld_cmd = 1;
req = 1;
clr_error = 1;
clr_done = 1;
if (bus_write==1)
begin
next_st = `WRITE_ST;
dir = 0;
end
else if(!bus_write)
begin
next_st = `READ_ST;
dir = 1;
end
end
else if(!bus_go)
next_st = `IDLE_ST;


`WRITE_ST: if (wready)
begin
next_st = `DONE_ST;
req = 0;
set_done = 1;
end
else if (timeout)
next_st = `ERROR_ST;
else if (!timeout)
next_st = `WRITE_ST;


`READ_ST: if(rready)
begin
latch_data = 1;
req = 0;
set_done = 1;
next_st = `DONE_ST;
end
else if (timeout)
next_st = `ERROR_ST;
else if (!timeout)
next_st = `READ_ST;


`DONE_ST: if (!bus_go)
begin
next_st = `IDLE_ST;
clr_done = 1;
end
else if (bus_go)
next_st = `DONE_ST;


`ERROR_ST: begin
set_error = 1;
set_done = 1;
next_st = `DONE_ST;
end


default: next_st = `IDLE_ST;

endcase
end



Thanks
Rik
 
The default for dir and req are dir and req from the blocking assignments
before the case statement. Within the case statement there is not a uniques
assignment for dir and req for every case. End result: if the case is
evaluated with no explicit assignment and the blocking assignment is used,
dir = dir; is a latch.


"rik" <ritwikbiswas@gmail.com> wrote in message
news:1162243167.534578.147240@h48g2000cwc.googlegroups.com...
I have this following state machine. My question is though I have
default values for all the signals, why "req" and "dir" is inferred as
latches?


always@ (pres_st, bus_go, bus_write, wready, rready, timeout)
begin
// State Machine defaults
latch_data = 0;
ld_cmd = 0;
set_error = 0;
clr_error = 0;
set_done = 0;
clr_done = 0;
req = req;
dir = dir;
case (pres_st)

`IDLE_ST: if (bus_go)
begin
ld_cmd = 1;
req = 1;
clr_error = 1;
clr_done = 1;
if (bus_write==1)
begin
next_st = `WRITE_ST;
dir = 0;
end
else if(!bus_write)
begin
next_st = `READ_ST;
dir = 1;
end
end
else if(!bus_go)
next_st = `IDLE_ST;


`WRITE_ST: if (wready)
begin
next_st = `DONE_ST;
req = 0;
set_done = 1;
end
else if (timeout)
next_st = `ERROR_ST;
else if (!timeout)
next_st = `WRITE_ST;


`READ_ST: if(rready)
begin
latch_data = 1;
req = 0;
set_done = 1;
next_st = `DONE_ST;
end
else if (timeout)
next_st = `ERROR_ST;
else if (!timeout)
next_st = `READ_ST;


`DONE_ST: if (!bus_go)
begin
next_st = `IDLE_ST;
clr_done = 1;
end
else if (bus_go)
next_st = `DONE_ST;


`ERROR_ST: begin
set_error = 1;
set_done = 1;
next_st = `DONE_ST;
end


default: next_st = `IDLE_ST;

endcase
end



Thanks
Rik
Click to expand...
 
Rik -

If you look at the default values for the 2 signals in question,
you'll see that you have req=req and dir=dir.

So, the synthesis tool says, if nothing overrides these default values,
hold the current value.

Hold the current value sounds a lot like a latch, correct?

If you had used req = 1 (or 0), then you wouldn't imply a latch.

John Providenza

rik wrote:
I have this following state machine. My question is though I have
default values for all the signals, why "req" and "dir" is inferred as
latches?


always@ (pres_st, bus_go, bus_write, wready, rready, timeout)
begin
// State Machine defaults
latch_data = 0;
ld_cmd = 0;
set_error = 0;
clr_error = 0;
set_done = 0;
clr_done = 0;
req = req;
dir = dir;
case (pres_st)

`IDLE_ST: if (bus_go)
begin
ld_cmd = 1;
req = 1;
clr_error = 1;
clr_done = 1;
if (bus_write==1)
begin
next_st = `WRITE_ST;
dir = 0;
end
else if(!bus_write)
begin
next_st = `READ_ST;
dir = 1;
end
end
else if(!bus_go)
next_st = `IDLE_ST;


`WRITE_ST: if (wready)
begin
next_st = `DONE_ST;
req = 0;
set_done = 1;
end
else if (timeout)
next_st = `ERROR_ST;
else if (!timeout)
next_st = `WRITE_ST;


`READ_ST: if(rready)
begin
latch_data = 1;
req = 0;
set_done = 1;
next_st = `DONE_ST;
end
else if (timeout)
next_st = `ERROR_ST;
else if (!timeout)
next_st = `READ_ST;


`DONE_ST: if (!bus_go)
begin
next_st = `IDLE_ST;
clr_done = 1;
end
else if (bus_go)
next_st = `DONE_ST;


`ERROR_ST: begin
set_error = 1;
set_done = 1;
next_st = `DONE_ST;
end


default: next_st = `IDLE_ST;

endcase
end



Thanks
Rik
Click to expand...
 
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