latch and shift 15 bits.

D

Denis Gleeson

Guest
Hello all

I am trying to implement the following logic in a xilinx XCS05xl
FPGA.

I have a 15 bit binary counter. I need to store its count value
on the occurrence of an event. Some time later I need to shift the stored
counter value out of the FPGA in a serial fashion under the control
of a clock.

What I currently have is:
-----------------------------------------------------------------------
input clear;
reg clear;

input ACB_Decade_Count_Enable;

input ACB_Read_Trigger_Address_Clk;

output ACB_Trigger_Address_Output;
reg ACB_Trigger_Address_Output;

reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.


// Store the count value when ACB_Decade_Count_Enable is high.
always @ (ACB_Decade_Count_Enable)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

// Now shift out the stored count serially.
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
begin
if(clear)
begin
ACB_Trigger_Address_Output <=0;
end
else
begin
ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
end
end

-----------------------------------------------------------------------

With this code my synthesis step gives the following errors.

Warning - Latch inferred in design "My block" read with
'hdlin_check_no_latch'(HDL - 307)

Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has more
than one driver(FPGA-CHECK-5)

The last error is repeated for all bits in Store_Trigger_Acquisition_Count.


The logic above seems correct in my head but Im not an FPGA expert.
Obviously I need a different implementation. Any suggestions.


Many thanks for all suggestions in advance.

Denis
 
dgleeson-2@utvinternet.com (Denis Gleeson) wrote in message news:<184c35f9.0311060253.19553d1f@posting.google.com>...

Hi,

You do have multiple drivers to Store_Trigger_Acquisition_Count.
One source is Out_acquisition_count and the other is the bit from
Store_Trigger_Acquisition_Count you are trying to shift. You need a
mux for each bit of register. I hope it helps.


Hello all

I am trying to implement the following logic in a xilinx XCS05xl
FPGA.

I have a 15 bit binary counter. I need to store its count value
on the occurrence of an event. Some time later I need to shift the stored
counter value out of the FPGA in a serial fashion under the control
of a clock.

What I currently have is:
-----------------------------------------------------------------------
input clear;
reg clear;

input ACB_Decade_Count_Enable;

input ACB_Read_Trigger_Address_Clk;

output ACB_Trigger_Address_Output;
reg ACB_Trigger_Address_Output;

reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.


// Store the count value when ACB_Decade_Count_Enable is high.
always @ (ACB_Decade_Count_Enable)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

// Now shift out the stored count serially.
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
begin
if(clear)
begin
ACB_Trigger_Address_Output <=0;
end
else
begin
ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
end
end

-----------------------------------------------------------------------

With this code my synthesis step gives the following errors.

Warning - Latch inferred in design "My block" read with
'hdlin_check_no_latch'(HDL - 307)

Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has more
than one driver(FPGA-CHECK-5)

The last error is repeated for all bits in Store_Trigger_Acquisition_Count.


The logic above seems correct in my head but Im not an FPGA expert.
Obviously I need a different implementation. Any suggestions.


Many thanks for all suggestions in advance.

Denis
Click to expand...
 
The problem is that you have assigned signal Store_Trigger_Acquisition_Count
in two processes.
One possible solution is the following ;

always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk )
begin
if(clear)
out_count <= 4'b1110;
else
out_count <= out_count - 1;
end

assign ACB_Trigger_Address_Output =
Store_Trigger_Acquisition_Count[out_count];


This solution creates a latch for Store_Trigger_Acquisition_Count and then
uses an internal down counter to mux the Output under control of the clock.


"Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message
news:184c35f9.0311060253.19553d1f@posting.google.com...
Hello all

I am trying to implement the following logic in a xilinx XCS05xl
FPGA.

I have a 15 bit binary counter. I need to store its count value
on the occurrence of an event. Some time later I need to shift the stored
counter value out of the FPGA in a serial fashion under the control
of a clock.

What I currently have is:
-----------------------------------------------------------------------
input clear;
reg clear;

input ACB_Decade_Count_Enable;

input ACB_Read_Trigger_Address_Clk;

output ACB_Trigger_Address_Output;
reg ACB_Trigger_Address_Output;

reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.


// Store the count value when ACB_Decade_Count_Enable is high.
always @ (ACB_Decade_Count_Enable)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

// Now shift out the stored count serially.
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
begin
if(clear)
begin
ACB_Trigger_Address_Output <=0;
end
else
begin
ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
end
end

-----------------------------------------------------------------------

With this code my synthesis step gives the following errors.

Warning - Latch inferred in design "My block" read with
'hdlin_check_no_latch'(HDL - 307)

Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has
more
than one driver(FPGA-CHECK-5)

The last error is repeated for all bits in
Store_Trigger_Acquisition_Count.


The logic above seems correct in my head but Im not an FPGA expert.
Obviously I need a different implementation. Any suggestions.


Many thanks for all suggestions in advance.

Denis
Click to expand...
 
Hi Chuck

Many thanks for your input on my question.
I have used your code and it leaves me with just one problem in my
simulator that you may be able to advise me on.

It is a warning that Net "/clear" does not set/reset
"/".../Store_trigger_Acquisition_Count_reg<0>
all other bits for Store_trigger_Acquisition_Count get the same
warning.

The result is that the synthesis tool warns that no global set/reset
(GSR) net could be used in the design as there is not a unique net
that sets or resets all the sequential cells.

I have modified your code to include the use of the clear signal to
set Store_Trigger_Acquisition_Count
to 0. This has had no effect.

Any suggestions?

always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count or clear)
if(clear)
Store_Trigger_Acquisition_Count <= 14'b0;
else
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk )
begin
if(clear)
out_count <= 4'b1110;
else
out_count <= out_count - 1;
end


Many thanks for your input.

Denis
"Chuck Levin" <clevin1234@comcast.net> wrote in message news:<u-udnRdzu_xrzDeiRVn-ug@comcast.com>...
The problem is that you have assigned signal Store_Trigger_Acquisition_Count
in two processes.
One possible solution is the following ;

always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk )
begin
if(clear)
out_count <= 4'b1110;
else
out_count <= out_count - 1;
end

assign ACB_Trigger_Address_Output =
Store_Trigger_Acquisition_Count[out_count];


This solution creates a latch for Store_Trigger_Acquisition_Count and then
uses an internal down counter to mux the Output under control of the clock.


"Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message
news:184c35f9.0311060253.19553d1f@posting.google.com...
Hello all

I am trying to implement the following logic in a xilinx XCS05xl
FPGA.

I have a 15 bit binary counter. I need to store its count value
on the occurrence of an event. Some time later I need to shift the stored
counter value out of the FPGA in a serial fashion under the control
of a clock.

What I currently have is:
-----------------------------------------------------------------------
input clear;
reg clear;

input ACB_Decade_Count_Enable;

input ACB_Read_Trigger_Address_Clk;

output ACB_Trigger_Address_Output;
reg ACB_Trigger_Address_Output;

reg [14:0] Store_Trigger_Acquisition_Count; // Storage for counter count.


// Store the count value when ACB_Decade_Count_Enable is high.
always @ (ACB_Decade_Count_Enable)
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end

// Now shift out the stored count serially.
always @ (posedge clear or posedge ACB_Read_Trigger_Address_Clk)
begin
if(clear)
begin
ACB_Trigger_Address_Output <=0;
end
else
begin
ACB_Trigger_Address_Output <=Store_Trigger_Acquisition_Count[14];
Store_Trigger_Acquisition_Count <= Store_Trigger_Acquisition_Count << 1;
end
end

-----------------------------------------------------------------------

With this code my synthesis step gives the following errors.

Warning - Latch inferred in design "My block" read with
'hdlin_check_no_latch'(HDL - 307)

Error - The net /../my block/Store_Trigger_Acquisition_Count<13> has
more
than one driver(FPGA-CHECK-5)

The last error is repeated for all bits in
Store_Trigger_Acquisition_Count.


The logic above seems correct in my head but Im not an FPGA expert.
Obviously I need a different implementation. Any suggestions.


Many thanks for all suggestions in advance.

Denis
Click to expand...
 
"Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message
news:184c35f9.0311070333.7a6acaae@posting.google.com...
Hi Chuck

Many thanks for your input on my question.
I have used your code and it leaves me with just one problem in my
simulator that you may be able to advise me on.

It is a warning that Net "/clear" does not set/reset
"/".../Store_trigger_Acquisition_Count_reg<0
all other bits for Store_trigger_Acquisition_Count get the same
warning.

The result is that the synthesis tool warns that no global set/reset
(GSR) net could be used in the design as there is not a unique net
that sets or resets all the sequential cells.

I have modified your code to include the use of the clear signal to
set Store_Trigger_Acquisition_Count
to 0. This has had no effect.

Any suggestions?

always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count or clear)
if(clear)
Store_Trigger_Acquisition_Count <= 14'b0;
else
Click to expand...
Shouldn't that be 15'b0?

Best regards,


Ben
 
In article <184c35f9.0311070333.7a6acaae@posting.google.com>, Denis
Gleeson <dgleeson-2@utvinternet.com> wrote:

always @ (ACB_Decade_Count_Enable or OUT_Acquisition_Count or clear)
if(clear)
Store_Trigger_Acquisition_Count <= 14'b0;
else
begin
if(ACB_Decade_Count_Enable) // event happened input is high.
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
end
Click to expand...
You have a fundamental problem here - the design is not synchrounous.
If ACB_Decade_Count_Enable is a synchronous signal created by your
system clock then you have a race condition here. If
OUT_Acquisition_Count changes before ACB_Decade_Count_Enable goes away,
you may not latch the proper data.

A better way would be the following:

always @(posedge clear or posedge clk)
if (clear)
Store_Trigger_Acquisition_Count <= 15'b0;
else
if (ACB_Decade_Count_Enable)
Store_Trigger_Acquisition_Count <= OUT_Acquisition_Count;
 
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