A
Amit
Guest
Hello group,
How should I create a Latch in VHDL?
Regards,
Amit
How should I create a Latch in VHDL?
Regards,
Amit
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A
Amit
Guest
On Jun 8, 12:05 am, Amit <amit.ko...@gmail.com> wrote:
OK. Let me give you more information. I know how to create a latch in
VDHL but what I don't know is that since we don't have a clock there
then how should I implement a situation that has different steps. Or
let's say an FSM situation?
All Latch has as input are data_input and enable_ctrl.
Your help will be appreciated greatly.
Thanks
Amit
Hello group,
How should I create a Latch in VHDL?
Regards,
Amit
OK. Let me give you more information. I know how to create a latch in
VDHL but what I don't know is that since we don't have a clock there
then how should I implement a situation that has different steps. Or
let's say an FSM situation?
All Latch has as input are data_input and enable_ctrl.
Your help will be appreciated greatly.
Thanks
Amit
J
JK
Guest
On Jun 8, 12:14 pm, Amit <amit.ko...@gmail.com> wrote:
If you want to have FSM situation on op, update data_input/enable_ctrl
signals in a FSM.
This FSM will work w.r.to clock. ie., enable_ctrl/data_input will
depend on FSM state.
Is this what you are expecting??
Regards,
JK
op <= data_input when enable_ctrl='1'; will create latch as expected.On Jun 8, 12:05 am, Amit <amit.ko...@gmail.com> wrote:
Hello group,
How should I create a Latch in VHDL?
Regards,
Amit
OK. Let me give you more information. I know how to create a latch in
VDHL but what I don't know is that since we don't have a clock there
then how should I implement a situation that has different steps. Or
let's say an FSM situation?
All Latch has as input are data_input and enable_ctrl.
Your help will be appreciated greatly.
Thanks
Amit
If you want to have FSM situation on op, update data_input/enable_ctrl
signals in a FSM.
This FSM will work w.r.to clock. ie., enable_ctrl/data_input will
depend on FSM state.
Is this what you are expecting??
Regards,
JK
A
Amit
Guest
On Jun 8, 12:25 am, JK <krishna.januman...@gmail.com> wrote:
Hello JK,
Are you saying that I can use the same FSM structure I have used in a
FlipFLop for the D-Latch?
Another words, should I check if the latch is Enable and then some
predefined values to the output?
like:
process(enable)
begin
if enable = '0' then
state_reg <= InitState;
elsif
state_reg <= State1;
end If;
end process;
Thanks for your response and time you spent.
Regards,
Amit
On Jun 8, 12:14 pm, Amit <amit.ko...@gmail.com> wrote:
On Jun 8, 12:05 am, Amit <amit.ko...@gmail.com> wrote:
Hello group,
How should I create a Latch in VHDL?
Regards,
Amit
OK. Let me give you more information. I know how to create a latch in
VDHL but what I don't know is that since we don't have a clock there
then how should I implement a situation that has different steps. Or
let's say an FSM situation?
All Latch has as input are data_input and enable_ctrl.
Your help will be appreciated greatly.
Thanks
Amit
op <= data_input when enable_ctrl='1'; will create latch as expected.
If you want to have FSM situation on op, update data_input/enable_ctrl
signals in a FSM.
This FSM will work w.r.to clock. ie., enable_ctrl/data_input will
depend on FSM state.
Is this what you are expecting??
Regards,
JK- Hide quoted text -
- Show quoted text -
Hello JK,
Are you saying that I can use the same FSM structure I have used in a
FlipFLop for the D-Latch?
Another words, should I check if the latch is Enable and then some
predefined values to the output?
like:
process(enable)
begin
if enable = '0' then
state_reg <= InitState;
elsif
state_reg <= State1;
end If;
end process;
Thanks for your response and time you spent.
Regards,
Amit
J
JK
Guest
On Jun 8, 12:58 pm, Amit <amit.ko...@gmail.com> wrote:
It is like this. Suppose that u r generating latch for signal op.
op <= data_input when enable_ctrl='1';
So, your op will be latched to data_input only when enable_ctrl='1';
Now, if you want FSM kind of states on signal op...
type states is (st0, st1, st2...);
signal state : states;
process(clk, reset)
begin
if reset='1' then
state <= st0;
enable_ctrl <= '0';
elsif rising_edge(clk) then
case state is
when st0 =>
state <= st1;
enable_ctrl <= '1';
when st1 =>
state <= st2;
enable_ctrl <= '0';
[...]
Now, you are controlling generation of enable_ctrl w.r.to a FSM, so
your signal op will be reflecting FSM states, though it is a latch.
Regards,
JK
No.Hello JK,
Are you saying that I can use the same FSM structure I have used in a
FlipFLop for the D-Latch?
Another words, should I check if the latch is Enable and then some
predefined values to the output?
like:
process(enable)
begin
if enable = '0' then
state_reg <= InitState;
elsif
state_reg <= State1;
end If;
end process;
Thanks for your response and time you spent.
Regards,
Amit- Hide quoted text -
- Show quoted text -
It is like this. Suppose that u r generating latch for signal op.
op <= data_input when enable_ctrl='1';
So, your op will be latched to data_input only when enable_ctrl='1';
Now, if you want FSM kind of states on signal op...
type states is (st0, st1, st2...);
signal state : states;
process(clk, reset)
begin
if reset='1' then
state <= st0;
enable_ctrl <= '0';
elsif rising_edge(clk) then
case state is
when st0 =>
state <= st1;
enable_ctrl <= '1';
when st1 =>
state <= st2;
enable_ctrl <= '0';
[...]
Now, you are controlling generation of enable_ctrl w.r.to a FSM, so
your signal op will be reflecting FSM states, though it is a latch.
Regards,
JK
A
Amit
Guest
On Jun 8, 1:16 am, JK <krishna.januman...@gmail.com> wrote:
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit
On Jun 8, 12:58 pm, Amit <amit.ko...@gmail.com> wrote:
Hello JK,
Are you saying that I can use the same FSM structure I have used in a
FlipFLop for the D-Latch?
Another words, should I check if the latch is Enable and then some
predefined values to the output?
like:
process(enable)
begin
if enable = '0' then
state_reg <= InitState;
elsif
state_reg <= State1;
end If;
end process;
Thanks for your response and time you spent.
Regards,
Amit- Hide quoted text -
- Show quoted text -
No.
It is like this. Suppose that u r generating latch for signal op.
op <= data_input when enable_ctrl='1';
So, your op will be latched to data_input only when enable_ctrl='1';
Now, if you want FSM kind of states on signal op...
type states is (st0, st1, st2...);
signal state : states;
process(clk, reset)
begin
if reset='1' then
state <= st0;
enable_ctrl <= '0';
elsif rising_edge(clk) then
case state is
when st0 =
state <= st1;
enable_ctrl <= '1';
when st1 =
state <= st2;
enable_ctrl <= '0';
[...]
Now, you are controlling generation of enable_ctrl w.r.to a FSM, so
your signal op will be reflecting FSM states, though it is a latch.
Regards,
JK- Hide quoted text -
- Show quoted text -
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit
P
Paul Uiterlinden
Guest
Amit wrote:
going to design. Is request edge sensitive or level sensitive? How should
the ack work? Why is it inout in stead of out?
must use latches" simply does not make any sense.
Depending on the requirement, I can imagine a design where the request
inputs are used as a clocks, capturing the positive edges on the request
inputs. It would not be a nice synchronous design though.
--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
Before doing anything, you need precise requirements of the block you areRight here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
going to design. Is request edge sensitive or level sensitive? How should
the ack work? Why is it inout in stead of out?
Why are you so focused on latches? The reasoning "there is no clock, so Ias you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
must use latches" simply does not make any sense.
Depending on the requirement, I can imagine a design where the request
inputs are used as a clocks, capturing the positive edges on the request
inputs. It would not be a nice synchronous design though.
--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
J
JK
Guest
On Jun 8, 1:28 pm, Amit <amit.ko...@gmail.com> wrote:
not need FSM in this case...
Regards,
JK
Amit, then it depends on what you want to send on ack. I guess you mayRight here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit- Hide quoted text -
- Show quoted text -
not need FSM in this case...
Regards,
JK
A
Amit
Guest
On Jun 8, 1:52 am, JK <krishna.januman...@gmail.com> wrote:
But how should I switch from one state to anohter one? if there is no
need for FSM. Would you give me small sample?
Regards,
Amit
Hi JK,On Jun 8, 1:28 pm, Amit <amit.ko...@gmail.com> wrote:
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit- Hide quoted text -
- Show quoted text -
Amit, then it depends on what you want to send on ack. I guess you may
not need FSM in this case...
Regards,
JK- Hide quoted text -
- Show quoted text -
But how should I switch from one state to anohter one? if there is no
need for FSM. Would you give me small sample?
Regards,
Amit
Guest
On Jun 8, 10:34 am, Amit <amit.ko...@gmail.com> wrote:
if a = '1' and c /= '0' then
d <= '00'
elsif a = '0' and c = '0' then
d <= '01'
end if;
Is this enough to get you going?
The if statement without else part would create a latch. For example,On Jun 8, 1:52 am, JK <krishna.januman...@gmail.com> wrote:
On Jun 8, 1:28 pm, Amit <amit.ko...@gmail.com> wrote:
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit- Hide quoted text -
- Show quoted text -
Amit, then it depends on what you want to send on ack. I guess you may
not need FSM in this case...
Regards,
JK- Hide quoted text -
- Show quoted text -
Hi JK,
But how should I switch from one state to anohter one? if there is no
need for FSM. Would you give me small sample?
Regards,
Amit- Hide quoted text -
- Show quoted text -
if a = '1' and c /= '0' then
d <= '00'
elsif a = '0' and c = '0' then
d <= '01'
end if;
Is this enough to get you going?
A
Amit
Guest
On Jun 8, 2:07 pm, willwestw...@gmail.com wrote:
Regards,
Amit
Thanks for sharing it but what is /= operator?On Jun 8, 10:34 am, Amit <amit.ko...@gmail.com> wrote:
On Jun 8, 1:52 am, JK <krishna.januman...@gmail.com> wrote:
On Jun 8, 1:28 pm, Amit <amit.ko...@gmail.com> wrote:
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit- Hide quoted text -
- Show quoted text -
Amit, then it depends on what you want to send on ack. I guess you may
not need FSM in this case...
Regards,
JK- Hide quoted text -
- Show quoted text -
Hi JK,
But how should I switch from one state to anohter one? if there is no
need for FSM. Would you give me small sample?
Regards,
Amit- Hide quoted text -
- Show quoted text -
The if statement without else part would create a latch. For example,
if a = '1' and c /= '0' then
d <= '00'
elsif a = '0' and c = '0' then
d <= '01'
end if;
Is this enough to get you going?- Hide quoted text -
- Show quoted text -
Regards,
Amit
Guest
On Jun 8, 4:32 pm, Amit <amit.ko...@gmail.com> wrote:
/= is does not equal, same as != in C.On Jun 8, 2:07 pm, willwestw...@gmail.com wrote:
On Jun 8, 10:34 am, Amit <amit.ko...@gmail.com> wrote:
On Jun 8, 1:52 am, JK <krishna.januman...@gmail.com> wrote:
On Jun 8, 1:28 pm, Amit <amit.ko...@gmail.com> wrote:
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit- Hide quoted text -
- Show quoted text -
Amit, then it depends on what you want to send on ack. I guess you may
not need FSM in this case...
Regards,
JK- Hide quoted text -
- Show quoted text -
Hi JK,
But how should I switch from one state to anohter one? if there is no
need for FSM. Would you give me small sample?
Regards,
Amit- Hide quoted text -
- Show quoted text -
The if statement without else part would create a latch. For example,
if a = '1' and c /= '0' then
d <= '00'
elsif a = '0' and c = '0' then
d <= '01'
end if;
Is this enough to get you going?- Hide quoted text -
- Show quoted text -
Thanks for sharing it but what is /= operator?
Regards,
Amit- Hide quoted text -
- Show quoted text -
A
Amit
Guest
On Jun 8, 5:13 pm, willwestw...@gmail.com wrote:
got it. Thanks
Regards,
Amit
On Jun 8, 4:32 pm, Amit <amit.ko...@gmail.com> wrote:
On Jun 8, 2:07 pm, willwestw...@gmail.com wrote:
On Jun 8, 10:34 am, Amit <amit.ko...@gmail.com> wrote:
On Jun 8, 1:52 am, JK <krishna.januman...@gmail.com> wrote:
On Jun 8, 1:28 pm, Amit <amit.ko...@gmail.com> wrote:
Right here is my problem. I don't have a clock!!! I must do this in
this entity:
entity arbiter is
port(
request: in std_logic_vector(0 to 3);
reset: in std_logic;
ack : inout std_logic_vector(0 to 3));
end entity arbiter;
as you see there is no clock even no enable signal. how can I
implement the FSM for this arbiter?
Regards,
Amit- Hide quoted text -
- Show quoted text -
Amit, then it depends on what you want to send on ack. I guess you may
not need FSM in this case...
Regards,
JK- Hide quoted text -
- Show quoted text -
Hi JK,
But how should I switch from one state to anohter one? if there is no
need for FSM. Would you give me small sample?
Regards,
Amit- Hide quoted text -
- Show quoted text -
The if statement without else part would create a latch. For example,
if a = '1' and c /= '0' then
d <= '00'
elsif a = '0' and c = '0' then
d <= '01'
end if;
Is this enough to get you going?- Hide quoted text -
- Show quoted text -
Thanks for sharing it but what is /= operator?
Regards,
Amit- Hide quoted text -
- Show quoted text -
/= is does not equal, same as != in C.- Hide quoted text -
- Show quoted text -
got it. Thanks
Regards,
Amit