Largest Write Burst to DDR2 Memories

R

Rajat Mitra

Guest
Hi all,
I am working on a design to optimize the write burst to DDR Memory for a
DDR2 Controller I have designed. Assuming that I have FIFO'ed an "N" number
of write operations and am going to burst the Write Requests to the DDR
Memory ( A Write Request (Wr) is - !CAS_N, !WE_N, !CS_N, COL_ADDR,
BANK_ADDR,DM(Data Mask)), what is the maximum number of Write Requests I can
send out to DDR ?? Currently I support only-
Wr->NOP->Wr; (2 Consecutive Writes - as per Micron and Samsung Spec. Sheets)
but would like to support something like -
Wr->NOP->Wr->NOP->Wr->NOP->Wr-NOP(i.e 4 Consecutive writes - is this
possible ?? ).

A Burst Write Request is ( On DDR Rising Clock Edge ) ->
Wr->NOP-Wr->NOP...... and within some Write Latency from the first Wr
Operation, the Write Data is clocked out ( Burts Size =4 ) on each edge of
the DDR Clock+delta; the DQS strobe edges strobing the data to the DDR
Memory.

Rajat Mitra
Freescale Semiconductors Inc.
 
Hi,
"2 Consecutive Writes - as per Micron and Samsung Spec. Sheets"

Please let me know where the sheet says that.

You can do as many as possible write, nop as you want in my opinion if
all data are in one same bank.

Weng
 
I tought so... as a matter of fact I should be able to do write > nop >
write > nod > write >nop indefinitely....not just to the same bank but to
open rows of each bank. While the data sheets don't explicitely say this,
the timing diagrams show only a write > nop > write >nop and this gave me
the wrong impression that a consecutive write could not be more than 2 back
to back...
Thanks for the clarification.

-Raj


<wtx@umem.com> wrote in message
news:1130290298.417906.305370@g14g2000cwa.googlegroups.com...
Hi,
"2 Consecutive Writes - as per Micron and Samsung Spec. Sheets"

Please let me know where the sheet says that.

You can do as many as possible write, nop as you want in my opinion if
all data are in one same bank.

Weng
 

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