Labels have no geometry error in Virtuoso

[AR]

When I extract my layout I get the error - "labels have no geometry",
with the markers just placed nowhere but in the dark space inside the
layout and I have only created the labels at the inputs and outputs,
where there are no markers. There are about 15 of them in the whole
layout. When I extract the layout without using the
parasitic_resistance and parasitic_capacitance switches then it gives
no error. The DRC is error free. How do I get rid of this problem?

Any help will be appreciated.

Thanks,
AR

 

[Gerry Vandevalk]

Condition 1)
Labels are connected to conductors when the label origin is over the
conductor.

Condition 2) Turning on parasitic_resistance typically invokes the PRE
function which
turns conductors into parasitic resistors except at "contacts" to the layer
and at "device" interface points.

Since condition 2 reduces the "valid" locations where labels can connect to
conductors, the person running extract with
parasitic resistance must understand why the labels have no connection to
the remaining conductors. ( The "layer" that had
a net name under the label is now considered to be somewhere on the body of
the parasitic resistor. ) It is somewhat
instructive to look at the conductors saved to the "extracted" rep (if the
kit bothers to save the conductors here. Not all do!)

A solution is to move these labels over top of "contacts" or "device"
connections ( or "layer" "pin")

With some more advanced kits, the inclusion of a "layer" that turns off
parasitics is available.
( I know, because I have coded several that do! )

-- Gerry Vandevalk.




"AR" <ashesh.rastogi@gmail.com> wrote in message
news:1131141174.935577.14670@g47g2000cwa.googlegroups.com...

When I extract my layout I get the error - "labels have no geometry",
with the markers just placed nowhere but in the dark space inside the
layout and I have only created the labels at the inputs and outputs,
where there are no markers. There are about 15 of them in the whole
layout. When I extract the layout without using the
parasitic_resistance and parasitic_capacitance switches then it gives
no error. The DRC is error free. How do I get rid of this problem?

Any help will be appreciated.

Thanks,
AR