Keystroke saving w/ IEEE.Numeric_Std

J

JustJohn

Guest
When you want a one of eight decoder, are you tired of typing in:

with Phase_Ctr
select Phase <=
"00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;

Then start taking advantage of IEEE.Numeric_Std:

Phase <= ROTATE_LEFT( "00000001", TO_INTEGER( Phase_Ctr ) );

This is equally clear, and should sim/synth just the same.

Other examples welcome...

Sidebar request to Xilinx:
I love the vhdl template your ISE produces when adding a new source,
but it still starts things off with:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

That is so '90s, we're over halfway through the 00's. Is there any way
to change your ISE vhdl template to:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

Regards all,
Just John
 
Thats pretty cool as long as synthesis tool correctly translates
it.!!!!
I have been using this function for indexing the std_logic arrays and
as memory pointers.....
 
Better to have 'Phase_Ctr' defined as a natural instead of a
std_logic_vector since that is how it is being used
i.e.
signal Phase_Ctr: natural range 0 to 7;

Then you have the even less cluttered

Phase <= ROTATE_LEFT( "00000001", Phase_Ctr );

As long as you remember to define the range properly (i.e. the 0 to 7) then
this will also synthesize to exactly the same thing.

"JustJohn" <john.l.smith@titan.com> wrote in message
news:1143578362.006883.143670@j33g2000cwa.googlegroups.com...
When you want a one of eight decoder, are you tired of typing in:

with Phase_Ctr
select Phase <=
"00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;

Then start taking advantage of IEEE.Numeric_Std:

Phase <= ROTATE_LEFT( "00000001", TO_INTEGER( Phase_Ctr ) );

This is equally clear, and should sim/synth just the same.

Other examples welcome...

Sidebar request to Xilinx:
I love the vhdl template your ISE produces when adding a new source,
but it still starts things off with:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

That is so '90s, we're over halfway through the 00's. Is there any way
to change your ISE vhdl template to:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

Regards all,
Just John
Click to expand...
 
+1 for natural type on phase_ctr!

Inside a process (sequential statements):

phase <= (others => '0'); -- sequential statements
phase(phase_ctr) <= '1';

Or if phase is a natural too:

phase <= 2**phase_ctr; -- sequential or concurrent assignment

Andy
 
Ashu wrote:
Thats pretty cool as long as synthesis tool correctly translates
it.!!!!
Click to expand...
I don't know of one that doesn't anymore.

I have been using this function for indexing the std_logic arrays and
as memory pointers.....
Click to expand...
Yes. For block ram templates.
I also like shift_left and rotate_left.
See vec_t and reg_v here.

http://home.comcast.net/~mike_treseler/sync_template.vhd

-- Mike Treseler
 
KJ wrote:
Better to have 'Phase_Ctr' defined as a natural instead of a
std_logic_vector since that is how it is being used
i.e.
signal Phase_Ctr: natural range 0 to 7;
Click to expand...
Yes sometimes a natural range counter is cleaner.
The downside is I lose the automatic rollover of unsigned.
Here are some related objects from
http://home.comcast.net/~mike_treseler/uart.vhd

constant roll_c : natural := tic_per_bit_c - 1;
subtype tic_count_t is natural range 0 to roll_c;
variable RxBitSampleCount_v : tic_count_t;
variable TxBitSampleCount_v : tic_count_t;
subtype bit_count_t is natural range 0 to char_len_c;
variable RxBitCount_v : bit_count_t;
variable TxBitCount_v : bit_count_t;

-- Mike Treseler
 
Andy wrote:
+1 for natural type on phase_ctr!

Inside a process (sequential statements):

phase <= (others => '0'); -- sequential statements
phase(phase_ctr) <= '1';

Or if phase is a natural too:

phase <= 2**phase_ctr; -- sequential or concurrent assignment

Andy
Click to expand...
Doh! This is great. (Sometimes I scare myself by how I miss the
simplest things). Thanks Andy.

Any more examples of keystroke/eye/paper savers out there?
 
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