JTAG questions

[aleksa]

When JTAG is used:
1. Is INIT_B driven LOW by FPGA?
2. Is INIT_B polled by FPGA to delay config?

The docs are a bit fuzzy about this.

 

[aleksa]

When JTAG is used:
1. Is INIT_B driven LOW by FPGA?
2. Is INIT_B polled by FPGA to delay config?

The docs are a bit fuzzy about this.

The questions are for Spartan 3A

 

[Gabor]

On Friday, March 4, 2011 7:30:57 AM UTC-5, aleksa wrote:

When JTAG is used:
1. Is INIT_B driven LOW by FPGA?

Yes. Right after power-on or after PROG_B de-assertion
INIT_B will be driven low while the FPGA config logic
initializes.

2. Is INIT_B polled by FPGA to delay config?

Yes. If you externally pull down INIT_B you can delay
the start of "master" config modes.

The docs are a bit fuzzy about this.

Aren't we all fuzzy at times