R
Rob Judd
Guest
Hi y'all,
Right, we're making some progress on parts sourcing, thanks in no small
way to some of you out there who shall remain nameless to avoid
embarrassment. (Thanks!)
What has come up next is the requirement for a JTAG programmer. I've
found one here:
http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm
but wonder whether using it on devices only capable of 3v3 or lower may
kill them. I'm also wondering whether some of the chips I'm considering
(Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx
XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs
that make a generic JTAG pod unworkable. If it merely requires level
translation, I'm golden.
Comments?
Rob
Right, we're making some progress on parts sourcing, thanks in no small
way to some of you out there who shall remain nameless to avoid
embarrassment. (Thanks!)
What has come up next is the requirement for a JTAG programmer. I've
found one here:
http://www.ee.latrobe.edu.au/~djc/PALS/SMALL_PALS.htm
but wonder whether using it on devices only capable of 3v3 or lower may
kill them. I'm also wondering whether some of the chips I'm considering
(Actel APA150, Altera EP1C3/EP1C6, Atmel AT94K05, Xilinx
XC2S200E/XC3S200 and Lattice OR3T80) have particular programming needs
that make a generic JTAG pod unworkable. If it merely requires level
translation, I'm golden.
Comments?
Rob