JTAG: JTAG_clock(0 or TMS); //last bit needs to have TMS act

[Veek M]

Could someone make sense of this code. Why is he OR'ing. My understanding of
the JTAG spec (i'm still reading it) was that:
1. You set state by driving the TMS-pin
2. You use the TDI pin to write data serially to the Instruction Register.

1. If he's using JTAG_clock to write data to the TMS pin and change state,
how is he using the same function to write to a different pin (TDI-pin).
2. Why the OR?

The spec is quite volumnious so if you can suggest any sort of
documents/sample-code to aid my understanding, please do.

http://www.fpga4fun.com/JTAG4.html
// Assuming that IR is 10 bits long,
// that there is only one device in the chain,
// and that SAMPLE code = 0000000101b
JTAG_clock(1);
JTAG_clock(0);
JTAG_clock(1);
JTAG_clock(0);
JTAG_clock(0);
JTAG_clock(0);
JTAG_clock(0);
JTAG_clock(0);
JTAG_clock(0);
JTAG_clock(0 or TMS); // last bit needs to have TMS active, to
exit shift-IR

// we are in Exit1-IR, go to Shift-DR
JTAG_clock(TMS);
JTAG_clock(TMS);
JTAG_clock(0);
JTAG_clock(0);