JTAG, CONF_DONE failed to go high in device 1.

[tramalo]

This is actually a re-post of my thread on alteraforum.com.
( www.alteraforum.com/forum/showthread.php?t=39255&p=161811#post161811 )
Having got no answers I'll post here as well.

Before anyone comments on this, I have searched the forum and rea
everything I have found on the internet with people getting this erro
message.
I'll try to post as much relevant information as possible, so the next on
who has this problem might get off a bit easier.

"Error (209014): CONF_DONE failed to go high in device 1"

The error message happens both when trying to program the Serial Flas
Loader and when trying to program JTAG directly. The programming fail
before there is any progress, it doesn't even say 0%.
Auto Detect Device functions as it should though. I get the choice betwee
EP4CE15 and EP3C16, but that has never been a problem with other designs.


I have made a custom board with a FBGA256 Cyclone IV EP4CE15 fpga and som
peripherals.
The fpga is hooked up with JTAG for Serial Flash Loader (SFL) as describe
in the Device Handbook on page 218 (figure 8-29, revision november 2011).


I'm using a 20MHz CMOS oscillator, although that shouldn't have any impac
on this issue as far as I know.


The supply voltages are derived through separate low-noise, high PSR
LDO-regulators which can deliver max 150mA each.
They are connected as such:
VCCIO of all IO-bank is 3,3V.
VCCINT is 1,2V.
VCCD_PLL and VCCA is 2,5V


nCE (J3) is connected to ground.
nStatus (F4), nConfig (H5) and CONF_DONE (H14) are all pulled to VCCIO b
10k resistors.


MSEL are connected as MSEL0(H13)=2,5V, MSEL1(H12)=GND, MSEL2(G12)=GND. Bu
since I'm using JTAG these would be overridden anyways.


The JTAG plug is connected as such:
1 - TCK (pin H3), pulled to GND by 1k
2 - GND
3 - TDO (pin J4)
4 - 2,5V
5 - TMS (pin J5), pulled to VCCIO by 10k
6 - 2,5V
7,8 - N.C.
9 - TDI (pin H4), pulled to VCCIO by 10k
10 - GND


Does anyone know anything I can try?



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[tramalo]

The supply voltages are derived through separate low-noise, high PSRR
LDO-regulators which can deliver max 150mA each.
They are connected as such:
VCCIO of all IO-bank is 3,3V.
VCCINT is 1,2V.
VCCD_PLL and VCCA is 2,5V

VCCD_PLL is actually 1,2V.

The JTAG plug is connected as such:
1 - TCK (pin H3), pulled to GND by 1k
2 - GND
3 - TDO (pin J4)
4 - 2,5V
5 - TMS (pin J5), pulled to VCCIO by 10k
6 - 2,5V
7,8 - N.C.
9 - TDI (pin H4), pulled to VCCIO by 10k
10 - GND

Pin 6 is actually a N.C. as well.
I have also tried pulling 5 and 9 to VCCA in stead with no effect.

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[tramalo]

Things I have noticed:
1. DEV_OE and INIT_DONE are each connected to a LED to ground with 470oh
resistors. They light up for a moment when I click the program-button i
the Device Programmer. They both give 3,3V.

- When INIT_DONE lights up, this should mean that the FPGA has entere
"User Mode". But what does it mean when it goes high for a moment and the
low again?
Might this be the registers initializing to a high value or something lik
that before configuration?

More things I have tried:
2. Checking the box for Compressed Bitstream. No change.
3. Enabling device-wide output enable (DEV_OE) and reset (DEV_CLRn) as pe
suggestions in another thread. No change.
4. Disconnecting the LEDs on DEV_OE and INIT_DONE, suspecting they'
overload the output. No change.
5. Tried pulling CONF_DONE high by a 1k resistor instead of 10k. N
change.

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