Johnson counter with decoder

[Prashanth simham]

Can i get verilog code for the johnson counter with decoder

 

[Johann Klammer]

On 04/17/2016 08:53 AM, Prashanth simham wrote:

Can i get verilog code for the johnson counter with decoder

Look at

Lessons in Electric circuits
Volume IV - Digital
sec 12.6.1

(it's on the web, google will find it)

 

[rickman]

On 4/17/2016 2:53 AM, Prashanth simham wrote:
> Can i get verilog code for the johnson counter with decoder

Crap! I wrote VHDL code before I saw you wanted Verilog. Can you
translate this? I haven't run it through a compiler, so it may have
bugs. In fact, it may not work at all. lol


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

ENTITY JohnsonCntr IS
GENERIC (
WIDTH : POSITIVE := 2
);
port(
clk : in std_logic;
rst : in std_logic;
JohnEnable : std_logic;
JohnOut : out unsigned(2*WIDTH - 1 downto 0)
);
END JohnsonCntr;

ARCHITECTURE behavior OF JohnsonCntr IS

signal JohnCntr : unsigned(WIDTH-1 downto 0);

BEGIN

-- Counter is synchronous
process(clk)
begin
if (rst) then
JohnCntr <= (others => '0');
elsif rising_edge(clk) then
if JohnEnable then
JohnCntr <= not JohnCntr(0) &JohnCntr(WIDTH-1 downto 1);
end if;
end if;
end process;

-- Decode is combinatorial
process(JohnCntr)
begin
JohnOut <= (others => '0');

JohnOut(0) <= not JohnCntr(0) and not JohnCntr(WIDTH-1);
JohnOut(WIDTH) <= JohnCntr(0) and JohnCntr(WIDTH-1);
FOR i in WIDTH-1 downto 1 loop
if (not JohnCntr(i) and not JohnCntr(i-1)) then
JohnOut (i) <= '1';
end if;
if (JohnCntr(i) and not JohnCntr(i-1)) then
JohnOut (i + WIDTH) <= '1';
end if;
end loop;
end process;

END;

--

Rick