P
pdx
Guest
How is the truth table for a JK flip flop derived from the circuit? I don't
understand it...
TIA.
understand it...
TIA.
J
John Popelish
Guest
pdx wrote:
http://www.play-hookey.com/digital/jk_nand_flip-flop.html
Note that there are two separate set reset flip flops (cross coupled
NANDs) connected in a loop by pairs of NAND gates. It functions
something like a shift register, copying the J K states into the first
RS flop during one clock state. When the clock goes to the other
state, it locks out changes in that flop and passes its state on to
the second R S flip flop. This lock and shift operation is what makes
it edge triggered.
--
John Popelish
Take a look at:
http://www.play-hookey.com/digital/jk_nand_flip-flop.html
Note that there are two separate set reset flip flops (cross coupled
NANDs) connected in a loop by pairs of NAND gates. It functions
something like a shift register, copying the J K states into the first
RS flop during one clock state. When the clock goes to the other
state, it locks out changes in that flop and passes its state on to
the second R S flip flop. This lock and shift operation is what makes
it edge triggered.
--
John Popelish
J
John Larkin
Guest
On Thu, 13 May 2004 19:31:34 +0100, "pdx" <pdx@spamtrap.com> wrote:
part or in an FPGA.
The classic TTL JKs would "catch ones"; if at any time the clock was
high and the J or K inputs went momentarily high in the "flip" sense,
it *would* flip on the next clock fall, even though the J/K had
returned low before the clock edge. Confused a lot of people.
John
Does anybody still use JKs? I haven't used one in years, as a single
part or in an FPGA.
The classic TTL JKs would "catch ones"; if at any time the clock was
high and the J or K inputs went momentarily high in the "flip" sense,
it *would* flip on the next clock fall, even though the J/K had
returned low before the clock edge. Confused a lot of people.
John
T
Tom Del Rosso
Guest
In news
c68a0pgalevqau7g7bbd9qk2mtmtirk41@4ax.com,
John Larkin typed:
D FF with some input logic, so that if neither J nor K was true then the
D input would revert to whatever level would not change the output?
--
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-and remove the obvious-
c68a0pgalevqau7g7bbd9qk2mtmtirk41@4ax.com,John Larkin typed:
Weren't there some that didn't ones-catch because they were made like a
D FF with some input logic, so that if neither J nor K was true then the
D input would revert to whatever level would not change the output?
--
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F
Fred Bloggs
Guest
John Larkin wrote:
parts with a strict master-slave architecture that specifically
prohibited certain input changes when the CLK was high. As for anyone
using them anymore, the JK was THE FF of choice for ASMs, whereas the D
FF was a natural for the much more versatile RTL architecture. The ASM
generally requires far more self-discipline than the average
semi-educated ape can muster, whereas the RTL is generalized enough to
absorb even the sloppiest quasi-thinking, hence the popularity of D's
and scarcity of JK's.
This has nothing to do with the JK-FF. The original TTL family had many
parts with a strict master-slave architecture that specifically
prohibited certain input changes when the CLK was high. As for anyone
using them anymore, the JK was THE FF of choice for ASMs, whereas the D
FF was a natural for the much more versatile RTL architecture. The ASM
generally requires far more self-discipline than the average
semi-educated ape can muster, whereas the RTL is generalized enough to
absorb even the sloppiest quasi-thinking, hence the popularity of D's
and scarcity of JK's.
J
John Larkin
Guest
On Fri, 14 May 2004 12:30:28 GMT, Fred Bloggs <nospam@nospam.com>
wrote:
possible way, just to show to the rest of the world how smart they
are.
John
wrote:
Absolutely right. Really smart people always do things the hardest
possible way, just to show to the rest of the world how smart they
are.
John
T
Tom Del Rosso
Guest
In news:40A4BBD4.8050102@nospam.com,
Fred Bloggs typed:
don't mean Resistor-Transistor-Logic because you use the term in
contrast to ASMs, like some other high-level architecture.
--
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Fred Bloggs typed:
What is this? Real-Time-Logic? Register Transfer Logic? Obviously you
don't mean Resistor-Transistor-Logic because you use the term in
contrast to ASMs, like some other high-level architecture.
--
-Reply in group, but if emailing add 2 more zeros-
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A
Active8
Guest
On Thu, 13 May 2004 19:31:34 +0100, pdx wrote:
inputs and don't care states and write the outputs.
Ever think of changing your major to biz ad?
--
Best Regards,
Mike
The same way that any truth table is derived. You list all possible
inputs and don't care states and write the outputs.
Ever think of changing your major to biz ad?
--
Best Regards,
Mike
J
John S. Dyson
Guest
In article <40A4BBD4.8050102@nospam.com>,
Fred Bloggs <nospam@nospam.com> writes:
help to save a significant amount of logic. Most of the circuits that
I did were small (10-20 gates), and at that level, saving a few gates
with a JK was definitely helpful. For 'random' logic, I seldom saw
a real reason for NOT using a JK. The major reason for not using a
JK might be related to a lack of understanding or 'design concepts'
to fully utilize them.
Nowadays, the times that I'd use a CMOS/TTL (non FPGA/PAL/ROM or
microprocessor) logic based design would be very limited.
John
Fred Bloggs <nospam@nospam.com> writes:
to remember that properly designed circuits with JK instead of D would
help to save a significant amount of logic. Most of the circuits that
I did were small (10-20 gates), and at that level, saving a few gates
with a JK was definitely helpful. For 'random' logic, I seldom saw
a real reason for NOT using a JK. The major reason for not using a
JK might be related to a lack of understanding or 'design concepts'
to fully utilize them.
Nowadays, the times that I'd use a CMOS/TTL (non FPGA/PAL/ROM or
microprocessor) logic based design would be very limited.
John
J
John Larkin
Guest
On Sat, 15 May 2004 00:12:02 +0000 (UTC), toor@iquest.net (John S.
Dyson) wrote:
whether the active edge of a clock was the rise or fall. Discrete
transistor flipflops tended to be NPN with diode steering logic, which
was falling-edge stuff. JKs tended to clock on the fall, and Ds on the
rise. Clearly you can't design clean synchronous logic with mixed
clock edges, and rising won, so the JKs were on the losing side.
flipflop thingies, and d-flops driven by lookup tables (disguised as
and gates) is a real clean way to do things.
John
Dyson) wrote:
In the early days of DTL/TTL/SUHL/Utilogic, there was no standard for
whether the active edge of a clock was the rise or fall. Discrete
transistor flipflops tended to be NPN with diode steering logic, which
was falling-edge stuff. JKs tended to clock on the fall, and Ds on the
rise. Clearly you can't design clean synchronous logic with mixed
clock edges, and rising won, so the JKs were on the losing side.
FPGA state mechines now tend to be one-hot structures, not classic 2^n
flipflop thingies, and d-flops driven by lookup tables (disguised as
and gates) is a real clean way to do things.
John
T
Tam/WB2TT
Guest
"Fred Bloggs" <nospam@nospam.com> wrote in message
news:40A4BBD4.8050102@nospam.com...
set/clear inputs.
Tam
news:40A4BBD4.8050102@nospam.com...
ones catching on the J and K also had interaction between the clock and the
set/clear inputs.
Tam
J
John S. Dyson
Guest
In article <EZ-dnQJsNfP4ejvdRVn-gQ@comcast.com>,
"Tam/WB2TT" <t-tammaru@c0mca$t.net> writes:
using a microcode rom (or equivalent), then the benefit probable became nil.
So the death of the JK advantage probably appeared with the use of large
ROM type devices (or the mostly better yet programmable logic or PAL
stuff.) AFAIR, many old design techniques made some of the
hazard issues alot less troublesome than if doing ad-hoc designs. One
always has to carefully review the eccentricities, however.
It has probably been 20yrs since my last state machine design with
traditional (now probably ancient) random logic. The amount of flexibility
provided by microprocessors (and/or gate arrays of one kind or another)
would probably push the random logic designs (e.g. with ASM type techniqes)
into a very narrow niche. Way back when I did some sequencer designs
in hardware (before significant tools were commonplace), the similarities
between hardware and software were apparent.
The discipline of using well architected 'state machines' in software
or in hardware does translate to/from the simple logic designs of the
past (e.g. where one might use a JK) through a state machine that would
implement an internet server. An ad-hoc programming technique could
certainly cause quality problems in a product, and the hazards of
an ad-hoc hardware design can also cause 'problems.'
Again, I saw the 'advantage' of using JK flip flops as mostly a gate
count economy (where it might have been a little false because of the
complexity of the JK flip-flop interface.) D flip flops were certainly
more intuitive, but all but one or two designs that used JKs were
designed using well structured techniques.
(Using SSI 'gates' might have given a speed advantage in the early
1980's for simple designs, but it is incredible that in the 10-20nsec
for propagation in a saturated logic gate a Pentium4 can probably
do approx 10 floating point multiplications. A 74ls (or even 74AS) cannot
do much in the amount of time that a P4 can do a significant amount
of computation.)
John
"Tam/WB2TT" <t-tammaru@c0mca$t.net> writes:
be substantial gate savings when using a JK vs D 'random' logic design. If
using a microcode rom (or equivalent), then the benefit probable became nil.
So the death of the JK advantage probably appeared with the use of large
ROM type devices (or the mostly better yet programmable logic or PAL
stuff.) AFAIR, many old design techniques made some of the
hazard issues alot less troublesome than if doing ad-hoc designs. One
always has to carefully review the eccentricities, however.
It has probably been 20yrs since my last state machine design with
traditional (now probably ancient) random logic. The amount of flexibility
provided by microprocessors (and/or gate arrays of one kind or another)
would probably push the random logic designs (e.g. with ASM type techniqes)
into a very narrow niche. Way back when I did some sequencer designs
in hardware (before significant tools were commonplace), the similarities
between hardware and software were apparent.
The discipline of using well architected 'state machines' in software
or in hardware does translate to/from the simple logic designs of the
past (e.g. where one might use a JK) through a state machine that would
implement an internet server. An ad-hoc programming technique could
certainly cause quality problems in a product, and the hazards of
an ad-hoc hardware design can also cause 'problems.'
Again, I saw the 'advantage' of using JK flip flops as mostly a gate
count economy (where it might have been a little false because of the
complexity of the JK flip-flop interface.) D flip flops were certainly
more intuitive, but all but one or two designs that used JKs were
designed using well structured techniques.
(Using SSI 'gates' might have given a speed advantage in the early
1980's for simple designs, but it is incredible that in the 10-20nsec
for propagation in a saturated logic gate a Pentium4 can probably
do approx 10 floating point multiplications. A 74ls (or even 74AS) cannot
do much in the amount of time that a P4 can do a significant amount
of computation.)
John
T
Tam/WB2TT
Guest
"John S. Dyson" <toor@iquest.net> wrote in message
news:c86sk8$1eb$1@news.iquest.net...
software, for instance, has models for JKs.
Tam
news:c86sk8$1eb$1@news.iquest.net...
Using CPLDs and gate arrays does not automatically eliminate JKs. The Xilinx
software, for instance, has models for JKs.
Tam
J
John Larkin
Guest
On Sun, 16 May 2004 05:02:01 +0000 (UTC), toor@iquest.net (John S.
Dyson) wrote:
Ds with ad-hoc async logic.
John
Dyson) wrote:
There's no reason to associate JKs with synchronous state machines and
Ds with ad-hoc async logic.
John
J
John S. Dyson
Guest
In article <ga5fa0d82njrv68a7hrbjj4o1n4t4dt2c4@4ax.com>,
John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> writes:
design techniques.) Really, back when SSI (esp TTL) was common, there
was almost NO excuse for using D over JK in random logic, except where
there wasn't an improvement in gate count.
For cases where the chip cost of JK doesn't create an advantage (probably
nowadays where the logic cost is more on an actual gate count and not chip
count), then the advantage of JKs is probably lessened.
In a way, a JK was a way of packing just a little more logic into the
flip-flop chip.
John
John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> writes:
conceptualize with ad-hoc designs (probably due to avoiding structured
design techniques.) Really, back when SSI (esp TTL) was common, there
was almost NO excuse for using D over JK in random logic, except where
there wasn't an improvement in gate count.
For cases where the chip cost of JK doesn't create an advantage (probably
nowadays where the logic cost is more on an actual gate count and not chip
count), then the advantage of JKs is probably lessened.
In a way, a JK was a way of packing just a little more logic into the
flip-flop chip.
John