jitter measurements in Cadence

[Tanuj Aggarwal]

HI,
I wanted to measure the peak to peak jitter for my PLL design. I
have a few questions. Can PSS analysis do it? I am confused as whether
PSS is used only to measure phase noise introduced due to the
transistors or can it be used to measure the system jitter after it
has locked. Or is eye diagram a better way. Or is there just some way
by which I can integrate the Frequency deviation?

 

[Andrew Beckett]

Tanuj Aggarwal wrote, on 08/05/09 23:41:

HI,
I wanted to measure the peak to peak jitter for my PLL design. I
have a few questions. Can PSS analysis do it? I am confused as whether
PSS is used only to measure phase noise introduced due to the
transistors or can it be used to measure the system jitter after it
has locked. Or is eye diagram a better way. Or is there just some way
by which I can integrate the Frequency deviation?

This can be done with PSS/Pnoise. There are however several ways it can be made
to be faster. If using recent IC5141 and MMSIM versions (say MMSIM71) there is a
flow "PLL Noise Aware flow" which is covered in the documentation, which is an
automated way of building models of each block in order to efficiently analyze
the noise of the whole PLL.

Also you might want to take a look at
http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf

Regards,

Andrew.