Ŕ
ŕîđĺď
Guest
Hi
I would like to better understand few issues concerning Jitter:
1. What is the mathematical connection between a certain level of jitter and
the expected BER due
For example, in SONET the allowed generated jitter is 0.01rms/ 0.1ptp UI.
can this jitter level be translated to a specific BER level ? if so,how
exactly (a practical calculated example will be appreciated) ? If not, where
does these figures came from?
2. If I can guess for myself, I would expect that such allowed jitter level
can guaranty that by pointers adjustments the BER will be kept very low. Is
there an allowed level of BER (or allowed hits during a specific period of
time) in the standard, or it is expected that no hit at all will occur at
such low jitter?
3. In medical equipment for example, where no hit is allowed at all, how
such a performance level can be guarantied ?
Is it done by requiring even lower jitter levels?
Or by errors correcting tools (FEC ..?) must be applied ?
other means?
4. What is the difference between random and deterministic jitter ?
What are the ways to fight each of these jitter types on board ?
I am familiar with "fighting tools" as PLL, good terminations, accurate
layout, proper clock buffers, etc. but are these tools can reduce both
jitter types, or there is a specific set of tools for each type , and if so,
what ?
I will appreciate any help on the above.
Thanks
Amnon
I would like to better understand few issues concerning Jitter:
1. What is the mathematical connection between a certain level of jitter and
the expected BER due
For example, in SONET the allowed generated jitter is 0.01rms/ 0.1ptp UI.
can this jitter level be translated to a specific BER level ? if so,how
exactly (a practical calculated example will be appreciated) ? If not, where
does these figures came from?
2. If I can guess for myself, I would expect that such allowed jitter level
can guaranty that by pointers adjustments the BER will be kept very low. Is
there an allowed level of BER (or allowed hits during a specific period of
time) in the standard, or it is expected that no hit at all will occur at
such low jitter?
3. In medical equipment for example, where no hit is allowed at all, how
such a performance level can be guarantied ?
Is it done by requiring even lower jitter levels?
Or by errors correcting tools (FEC ..?) must be applied ?
other means?
4. What is the difference between random and deterministic jitter ?
What are the ways to fight each of these jitter types on board ?
I am familiar with "fighting tools" as PLL, good terminations, accurate
layout, proper clock buffers, etc. but are these tools can reduce both
jitter types, or there is a specific set of tools for each type , and if so,
what ?
I will appreciate any help on the above.
Thanks
Amnon