B
Bobby
Guest
I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.
Questions:
(1) Considering my end goal, i.e. to generate SV TB,
a java parser would be better or python ?
(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in SV for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?
(3) Any technique to go on further with java parser ?
Looking forward for suggestions
Questions:
(1) Considering my end goal, i.e. to generate SV TB,
a java parser would be better or python ?
(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in SV for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?
(3) Any technique to go on further with java parser ?
Looking forward for suggestions