Iverilog - Generate statement

[pkg]

Hi all,

Can someone tell what is the substitute for the 'generate' statement in
Iverilog. It seems to be giving an error whenever I use it.

Modelsim however is compiling it and doesnt report any error.

 

[Allan Herriman]

On 10 Mar 2006 20:50:11 -0800, "pkg" <pratikg@gmail.com> wrote:

Hi all,

Can someone tell what is the substitute for the 'generate' statement in
Iverilog. It seems to be giving an error whenever I use it.

There is no direct substitute. Iverilog does not support the current
version of the language. Most (all?) other tools do, and Iverilog is
very much in the minority here.

Your choices:
1) Don't use Iverilog.
2a) Convince the Iverilog author to fix the problem.
2b) Fix it yourself, and submit a patch to the Iverilog author.
3) Rewrite your code so that it doesn't use generate.

In the latter case, you might be able to use condition compilation to
solve your problem.

Modelsim however is compiling it and doesnt report any error.

As it should, assuming your code is correct.

Regards,
Allan

 

[Ajeetha]

Yet another option: Use a pre-processor, a quick googling revealed:

http://www.ics.mq.edu.au/~spon/verilog/

I remember there was one VPP for free, google it.

HTH
Ajeetha, CVC
www.noveldv.com

 

[Stephen Williams]

Allan Herriman wrote:

On 10 Mar 2006 20:50:11 -0800, "pkg" <pratikg@gmail.com> wrote:

Hi all,

Can someone tell what is the substitute for the 'generate' statement in
Iverilog. It seems to be giving an error whenever I use it.

There is no direct substitute. Iverilog does not support the current
version of the language. Most (all?) other tools do, and Iverilog is
very much in the minority here.

Yeah, yeah, I hear ya

It's on my list. There has been plenty of interest in generate,
so I'm getting it from all corners. I have paid tasks to work on
first, though.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[ngsayjoe@gmail.com]

Or you can try other Verilog simulator

-Joe

LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com




pkg wrote:

Hi all,

Can someone tell what is the substitute for the 'generate' statement in
Iverilog. It seems to be giving an error whenever I use it.

Modelsim however is compiling it and doesnt report any error.

 

[Stephen Williams]

ngsayjoe@gmail.com wrote:

Or you can try other Verilog simulator

-Joe

LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Ah yes, the free-for-now beta-of-a-commercial-product Window-XP-only
simulator that Joe tried to advertise here a month ago;-)

The point is valid, though: If the open-source tools don't cut
it for you (yet), and it is worth it for you, then by all means
go with a commercial tool. Commercial vendors try to make it worth
your money by making their product better somehow.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Erik de Castro Lopo]

Stephen Williams wrote:

Ah yes, the free-for-now beta-of-a-commercial-product Window-XP-only
simulator that Joe tried to advertise here a month ago;-)

The point is valid, though: If the open-source tools don't cut
it for you (yet), and it is worth it for you, then by all means
go with a commercial tool. Commercial vendors try to make it worth
your money by making their product better somehow.

Or even better, come to some arrangement with Steve here
to get the features you want implemented .

Erik
--
+-----------------------------------------------------------+
Erik de Castro Lopo
+-----------------------------------------------------------+
"Visual SourceSafe? It would be safer to print out all your code,
run it through a shredder, and set it on fire."
http://www.wadhome.org/svn_vs_vss.txt