istantiating an array port referring to individual (or group

[Andy Luotto]

hi there
hi ahave a module like
module the_module(input a[2:0], output z)

and i would like to assign individual signal to input (which is
allowed by vhdl). i tried both

wire x,y,z;
the_module i_module (.a[2](x), .a[1],.a[0](z));

but i get a syntax error

obviosly this

the_module i_module (.a({x,y,z} );

should work but i have a script which buoild a top level which i would
not modify

thanks

 

[pallav]

On Oct 22, 9:47 am, Andy Luotto <andyluo...@excite.com> wrote:

hi there
hi ahave a module like
module the_module(input a[2:0], output z)

and i would like to assign individual signal to input (which is
allowed by vhdl). i tried both

wire x,y,z;
the_module i_module (.a[2](x), .a[1],.a[0](z));

but i get a syntax error

obviosly this

the_module i_module (.a({x,y,z} );

should work but i have a script which buoild a top level which i would
not modify

thanks

You can say:

wire [2:0] in = {x, y, z};
the_module foo(.a(in));

You probably will have to modify the script to generate this.