Issues using files in VHDL

[Subramanian Ramaswamy]

I am trying to initialize a 16 bit shift register from a file which contains
"0000000000000000" using the following code. However, when simulating the
value in the file is not absorbed into the output or to the variable "val"
that I have used. If some one can help me figure out what the problem is, I
would appreciate it.

Thanks.

library IEEE;


use IEEE.STD_LOGIC_1164.all;
use std.textio.all;
entity ShiftReg is
Port (d_in : in std_logic_vector(15 downto 0);
serial_in,ld,shift,clk,reset : in std_logic;
q : inout std_logic_vector(15 downto 0));
end entity ShiftReg;

architecture behavioral of ShiftReg is
subtype word is std_logic_vector(15 downto 0);
type initz is file of word;
begin
P: process (clk, shift, ld,reset)
file datain : initz open read_mode is "init.txt";

begin
if (reset='1') then
while not(endfile(datain)) loop
read(datain,val);
end loop;
q <=val;
elsif ( clk'event and clk ='1') then
if (shift = '0') and (ld='1') then
q <= d_in ;
elsif (shift = '1') then
q(14 downto 0) <= q(15 downto 1) ;
q(15) <= serial_in ;
end if;
end if;
end process P;
end architecture behavioral;

 

[VhdlCohen]

architecture behavioral of ShiftReg is
subtype word is std_logic_vector(15 downto 0);
type initz is file of word;
begin
P: process (clk, shift, ld,reset)
file datain : initz open read_mode is "init.txt";

begin
if (reset='1') then
while not(endfile(datain)) loop
read(datain,val);
end loop;

You need a line declaration, and a readline before the read.
Thus:
begin
P: process (clk, shift, ld,reset)
file datain : initz open read_mode is "init.txt";
variable L : Line; -- NEW

begin
if (reset='1') then
while not(endfile(datain)) loop
readline(datain, L); -- NEW, read a line into L
read(L,val); -- Changed, read from Line into your variable
end loop;

----
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
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* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[Srinivasan Venkataramanan]

Hi,

"VhdlCohen" <vhdlcohen@aol.com> wrote in message
news:20030626171430.04605.00002093@mb-m21.aol.com...
<SNIP>>

You need a line declaration, and a readline before the read.
Thus:
begin
P: process (clk, shift, ld,reset)
file datain : initz open read_mode is "init.txt";
variable L : Line; -- NEW

Not sure if that's enough, as the file being opened is NOT of TEXT type, a
new type named "initz", in which case the predefined/overloaded by TEXTIO
procedures *may* not work. Infact I tried it and Modelsim 5.4 doesn't
compile (neither does NC), as a general suggestion the OP (Original Poster)
may want to stick to TEXT file type. (I am sure that Ben already knows this
problem and much much more).

begin
if (reset='1') then
while not(endfile(datain)) loop
readline(datain, L); -- NEW, read a line into L
read(L,val); -- Changed, read from Line into your variable

Another good idea would be to use the GOOD flag returned by the READ
procedure, it can help in catching any erros in the READ procedure.

Regards,
Srinivasan

end loop;

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel