U
unfrostedpoptart
Guest
Hi all.
This has been giving me headaches as I start using SV Interfaces.
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.
Does anyone have an easy solution to this? I could write a dummy
wrapper module, but I do this on dozens of different files, and that
starts becoming a lot of work. I thought of some PERL script to
automatically create this wrapper, but I'm not the best PERL
programmer, so it would take me a long time to get it working.
Thanks for any solutions / suggestions,
David
This has been giving me headaches as I start using SV Interfaces.
Here's the issue. The spec, and VCS, say it's illegal to have
unconnected ports of type interface. Normally, this isn't a problem.
I'd either have a higher-level RTL module that connects the ports, or
a testbench above the module that connects them. The problem is when I
want to do a quick compile on just that module while developing it to
check syntax, etc. I can't do this because VCS, and presumably other
compilers, error out on the unconnected interface ports.
Does anyone have an easy solution to this? I could write a dummy
wrapper module, but I do this on dozens of different files, and that
starts becoming a lot of work. I thought of some PERL script to
automatically create this wrapper, but I'm not the best PERL
programmer, so it would take me a long time to get it working.
Thanks for any solutions / suggestions,
David