ISM Simulation never finishes

[Nevo]

Hello all!

I'm new to FPGA's and am using Xilinx WebPack 8.2.01i to design and simulate
my design. (Running on WinXP SP2 with 1GB RAM.) I'm finding that the
simulation engine doesn't seem to be very reliable. Is that something others
have discovered as well?

For instance, I've got a fairly simple module for which I've created a
testbench waveform. When I try to generate simulation output, however, the
ISM engine appears to be instantiated but never finishes. The console output
shows this when I select "Generate Expected Simulation Results:"

WARNINGrojectMgmt - "C:/Documents and Settings/Nevo/My
Documents/Xilinx/testproj/DimmerClockGenerator/DimmerClockGenerator.ant"
line 21 duplicate design unit: 'Module|DimmerClockGenerator'
Running Fuse ...
Compiling project file "DimmerClockGenerator_gen.prj"
Compiling verilog file "C:\Documents and Settings\Nevo\My
Documents\Xilinx\testproj\DimmerClockGenerator/DimmerClockGenerator.v" in
library work
Module <DimmerClockGenerator> compiled
Parsing C:\Documents and Settings\Nevo\My
Documents\Xilinx\testproj\DimmerClockGenerator/DimmerClockGenerator.v: 0.15
Codegen work/DimmerClockGenerator: 1.49
Compiling verilog file "C:\Documents and Settings\Nevo\My
Documents\Xilinx\testproj\DimmerClockGenerator/DimmerClockGenerator.ant" in
library work
Module <DimmerClockGenerator> compiled
WARNING:HDLParsers:3215 - Unit work/DimmerClockGenerator is now defined in a
different file: was C:/Documents and Settings/Nevo/My
Documents/Xilinx/testproj/DimmerClockGenerator/DimmerClockGenerator.v, now
is C:/Documents and Settings/Nevo/My
Documents/Xilinx/testproj/DimmerClockGenerator/DimmerClockGenerator.ant
Parsing C:\Documents and Settings\Nevo\My
Documents\Xilinx\testproj\DimmerClockGenerator/DimmerClockGenerator.ant:
0.27
Codegen work/DimmerClockGenerator: 3.12
Building DimmerClockGenerator_tbxr.exe
Running ISim simulation engine ...


....and that's it. The CPU usage goes to 100% when the simulation engine
starts, but shortly after (1 second or so) goes to idle and I never get any
output from the simulator.

Even more bizarre, when I highlight the .tbw file and right-click "Simulate
Beahvioral Model," the envorinment *removes my Verilog file from the
project*! That can't be expected behavior, can it?

The module has a DCM that uses a 50MHz input clock to generate a 32MHZ
output from the CLKFX output, then a divide-by-8 circuit to give a 2MHz
output. That's all that's in the module.

Is there any way to coax the simulator to finish the simulation and give me
output?

Thanks,

Nevo