ISIM simulation speed

[Przemysław Elias]

Hi,

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?

Thanks in advance.

 

[Hal Murray]

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?

I'd like to add, that ISIM uses as little as 5-10% of my CPU during
that simulation. Simulating other modules takes 100% CPU and
consequenty much less time.

More memory.

--
These are my opinions, not necessarily my employer's. I hate spam.

 

[Przemysław Elias]

On 14 Gru, 10:51, Przemysław Elias <pempus...@gmail.com> wrote:

Hi,

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?

Thanks in advance.

I'd like to add, that ISIM uses as little as 5-10% of my CPU during
that simulation. Simulating other modules takes 100% CPU and
consequenty much less time.

 

[HT-Lab]

"Przemysław Elias" <pempushek@gmail.com> wrote in message
news:94013131-6fdf-4483-a8ab-0b6979219dc8@29g2000yqq.googlegroups.com...
On 14 Gru, 10:51, Przemysław Elias <pempus...@gmail.com> wrote:

Hi,

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?

Thanks in advance.

I'd like to add, that ISIM uses as little as 5-10% of my CPU during
that simulation. Simulating other modules takes 100% CPU and
consequenty much less time.

Are you using the full version? if not then you might have hit the limit,

Q. What is ISE Simulator Lite?
A. ISE Simulator Lite is a limited version of the ISE Simulator. There is only
one limitation. When the user design + testbench exceeds 50,000 lines of HDL
code, the simulator will start to derate the performance of the simulator for
that invocation.

http://www.xilinx.com/products/design_tools/logic_design/verification/ise_simulator_faq.htm

Hans
www.ht-lab.com

 

[Przemysław Elias]

On 14 Gru, 11:49, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?
I'd like to add, that ISIM uses as little as 5-10% of my CPU during
that simulation. Simulating other modules takes 100% CPU and
consequenty much less time.

More memory.

--
These are my opinions, not necessarily my employer's.  I hate spam.

That sounds like a solution, but this simulation is taking 300MB out
of my 4GB at the moment. Are you sure that more memory would help?
Aren't there any other solutions?

 

[Przemysław Elias]

On 14 Gru, 15:45, "HT-Lab" <han...@ht-lab.com> wrote:

"Przemys aw Elias" <pempus...@gmail.com> wrote in message

news:94013131-6fdf-4483-a8ab-0b6979219dc8@29g2000yqq.googlegroups.com...
On 14 Gru, 10:51, Przemys aw Elias <pempus...@gmail.com> wrote:

Hi,

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?

Thanks in advance.
I'd like to add, that ISIM uses as little as 5-10% of my CPU during
that simulation. Simulating other modules takes 100% CPU and
consequenty much less time.

Are you using the full version? if not then you might have hit the limit,

Q. What is ISE Simulator Lite?
A. ISE Simulator Lite is a limited version of the ISE Simulator. There is only
one limitation. When the user design + testbench exceeds 50,000 lines of HDL
code, the simulator will start to derate the performance of the simulator for
that invocation.

http://www.xilinx.com/products/design_tools/logic_design/verification...

Hanswww.ht-lab.com

Look's like this is an issue. I've got ISim from WebPack which is Lite
Version. Thanks for pointing this out!

 

[Petter Gustad]

"HT-Lab" <hans64@ht-lab.com> writes:

one limitation. When the user design + testbench exceeds 50,000 lines of HDL

Then something like this would get around the limitation:

find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\1/' | tr -d "\n\r" > oneliner.vhd

I always thought the limitation was given as a number of hdl
tokens/statements.

Petter

--
..sig removed by request.

 

[rickman]

On Dec 15, 4:00 am, Petter Gustad <newsmailco...@gustad.com> wrote:

"HT-Lab" <han...@ht-lab.com> writes:
one limitation. When the user design + testbench exceeds 50,000 lines of HDL

Then something like this would get around the limitation:

find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\1/' | tr -d "\n\r" > oneliner.vhd

I always thought the limitation was given as a number of hdl
tokens/statements.

It is. They don't count YOUR lines, they parse the code and count
what THEY consider to be lines.

I am VERY surprised that Xilinx is crippling their own simulator!!!
Isim is a Xilinx product no? So where is the marketing advantage to
slowing down your simulations when you are working with larger code
and most likely larger devices???

Do they really think it is a good idea to give away software that
discourages the use of their larger part$?

Rick

 

[Gabor]

On Dec 15, 9:32 am, rickman <gnu...@gmail.com> wrote:

On Dec 15, 4:00 am, Petter Gustad <newsmailco...@gustad.com> wrote:

"HT-Lab" <han...@ht-lab.com> writes:
one limitation. When the user design + testbench exceeds 50,000 lines of HDL

Then something like this would get around the limitation:

find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\1/' | tr -d "\n\r" > oneliner.vhd

I always thought the limitation was given as a number of hdl
tokens/statements.

It is.  They don't count YOUR lines, they parse the code and count
what THEY consider to be lines.

I am VERY surprised that Xilinx is crippling their own simulator!!!
Isim is a Xilinx product no?  So where is the marketing advantage to
slowing down your simulations when you are working with larger code
and most likely larger devices???

Do they really think it is a good idea to give away software that
discourages the use of their larger part$?

Rick

They must, since the Webpack does not support synthesis for the larger
parts either...

 

[Brian Drummond]

On Wed, 15 Dec 2010 06:32:41 -0800 (PST), rickman <gnuarm@gmail.com> wrote:

On Dec 15, 4:00 am, Petter Gustad <newsmailco...@gustad.com> wrote:
"HT-Lab" <han...@ht-lab.com> writes:
one limitation. When the user design + testbench exceeds 50,000 lines of HDL

Then something like this would get around the limitation:

find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\1/' | tr -d "\n\r" > oneliner.vhd

I always thought the limitation was given as a number of hdl
tokens/statements.

It is. They don't count YOUR lines, they parse the code and count
what THEY consider to be lines.

I am VERY surprised that Xilinx is crippling their own simulator!!!
Isim is a Xilinx product no? So where is the marketing advantage to
slowing down your simulations when you are working with larger code
and most likely larger devices???

The un-crippled version only adds about $1000 to the price of the un-crippled
toolset as a whole ($2400 -> $3400 approx ) and in my opinion it's pretty good
value, as opposed to the price of a retail Modelsim seat.

It's buggier, but it works cross-language and cross-platform. (and even if you
never touch Verilog, you still need to sim it because vendors don't supply VHDL
models of DDR2 memories...)

What doesn't help is Xilinx's insistence on supplying gate-level sim models for
key components (e.g. PCIe interface - AND its testbench!) - this means the 50k
line limit is crossed before a single line of application is written...

- Brian

 

[Kolja Sulimma]

On 14 Dez., 10:51, Przemysław Elias <pempus...@gmail.com> wrote:

Hi,

I've got some logic to simulate in ISIM. The problem is that it's
quite complex and it takes 9 hours to simulate on my laptop. Is there
any option that could help me gain a little speed-up?

Use std_ulogic instead of std_logic.

Kolja

 

[Andy Peters]

On Dec 15, 7:32 am, rickman <gnu...@gmail.com> wrote:

I am VERY surprised that Xilinx is crippling their own simulator!!!
Isim is a Xilinx product no?  So where is the marketing advantage to
slowing down your simulations when you are working with larger code
and most likely larger devices???

Short (and fully correct answer): They want you to buy the full-up
software.

Their assumption has always been that if you can afford to use the
largest devices in a design, then you can afford the full-up tools
required to design them in, on the theory that these larger designs
will require more support, which is paid for by buying the full-up
software.

Of course that's absurd. What Xilinx should really do is what Apple
does for support. The tools are free. But if you want support, you
choose either the free mailing lists, or you can pay for different
levels/amounts of support. So you can pay, in advance, for three or
four support 'incidents,' and the advantage here is that you get in
touch with someone on the first level that can actually help you, as
opposed to having to deal with the first-line drones, which wastes
days until you can convince them to escalate the problem (you
generally need to get your FAE involved).

Anyways, ISIM is cheaper than Active-HDL and ModelSim, but that makes
sense, because it's not ready for prime time yet.

-a