J
Jürgen Böhm
Guest
Hi,
I just downloaded and installed Xilinx ISEWebpack 12.4 on a machine
running Kubuntu 10.04 as a 64bit system. As a test for the new system I
started with a usual "Hello World" program in Verilog:
module main(sw, btn, led, clk, rst);
input rst;
input[7:0] sw;
input[3:0] btn;
output[7:0] led;
input clk;
reg[28:0] cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
cnt <= 0;
end
else
begin
cnt <= cnt + 1;
end
end
assign led = cnt[28:21] & sw;
endmodule
(I know btn's are unused, they are in for later use)
I could synthesize, map, place and route this, and finally generate a
main.bit file. Just two problems remained:
1) Although after some wrestling with cable drivers I got the Digilent
Cable (type 3) to my Spartan 3 Starter Kit from Digilent recognized and
could see the graphical representation of the JTAG chain on the IMPACT
screen, nevertheless it was impossible to program successfully: Always
there remained "9 errors" in the verified bitstream, even when the board
after the failed programming started working as expected.
2) What I found very annoying is, that, using the RTL schematic viewer
to display the above design, there always remains an error in the
schematic: The counter module inferred from the always block is shown
mostly unconnected, only clk is connected, the output Q and the input
port_data are unconnected. Also there is no connection from rst to the
counter module. This could not be overcome by zooming in.
Three years ago I completed a larger hobby project using WindowXP and
WebPack 8.1 and never experienced problems like that in 2). Just two
verify that my board is not defect after the error messages in 1) I
reverted to the old Windows version of the WebPack and indeed could
transfer the .bit file without failure.
Does anyone have an idea what is the cause for problem 2) and how to
overcome it? Is it a specific Linux related issue? The same question I
could ask for 1): It seems to be so near to working, but I do not know
what to try to make it from 99% success to 100% success. If needed I
could post output lines from the IMPACT tool.
Greetings
Jürgen
--
Jürgen Böhm www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?" R. Thom
I just downloaded and installed Xilinx ISEWebpack 12.4 on a machine
running Kubuntu 10.04 as a 64bit system. As a test for the new system I
started with a usual "Hello World" program in Verilog:
module main(sw, btn, led, clk, rst);
input rst;
input[7:0] sw;
input[3:0] btn;
output[7:0] led;
input clk;
reg[28:0] cnt;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
cnt <= 0;
end
else
begin
cnt <= cnt + 1;
end
end
assign led = cnt[28:21] & sw;
endmodule
(I know btn's are unused, they are in for later use)
I could synthesize, map, place and route this, and finally generate a
main.bit file. Just two problems remained:
1) Although after some wrestling with cable drivers I got the Digilent
Cable (type 3) to my Spartan 3 Starter Kit from Digilent recognized and
could see the graphical representation of the JTAG chain on the IMPACT
screen, nevertheless it was impossible to program successfully: Always
there remained "9 errors" in the verified bitstream, even when the board
after the failed programming started working as expected.
2) What I found very annoying is, that, using the RTL schematic viewer
to display the above design, there always remains an error in the
schematic: The counter module inferred from the always block is shown
mostly unconnected, only clk is connected, the output Q and the input
port_data are unconnected. Also there is no connection from rst to the
counter module. This could not be overcome by zooming in.
Three years ago I completed a larger hobby project using WindowXP and
WebPack 8.1 and never experienced problems like that in 2). Just two
verify that my board is not defect after the error messages in 1) I
reverted to the old Windows version of the WebPack and indeed could
transfer the .bit file without failure.
Does anyone have an idea what is the cause for problem 2) and how to
overcome it? Is it a specific Linux related issue? The same question I
could ask for 1): It seems to be so near to working, but I do not know
what to try to make it from 99% success to 100% success. If needed I
could post output lines from the IMPACT tool.
Greetings
Jürgen
--
Jürgen Böhm www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?" R. Thom